High voltage polysilicon gate in high-K metal gate device
An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm 2 . Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.
1. An integrated circuit (IC) comprising:
a semiconductor substrate comprising a memory area and a periphery area;
a memory device in the memory area;
a plurality of metal gates in the periphery area, each comprising a metal electrode and a high-κ dielectric; and
a plurality of polysilicon gates in the periphery area, each comprising a polysilicon electrode, a channel region, and one or more dielectrics spanning from the channel region to the polysilicon electrode;
wherein each of the one or more dielectrics of the polysilicon gates has a dielectric constant that is lower than that of any high-κ dielectric;
the polysilicon electrodes have larger areas area than the metal electrodes;
the polysilicon electrodes have top surfaces that are coplanar with top surfaces of the metal electrodes; and
one or more of the plurality of polysilicon gates is a high voltage device.
2. An IC according to claim 1 , wherein the memory device is embedded flash memory.
3. An IC according to claim 1 , wherein the one or more dielectrics have a thickness greater than a thickness of the high-κ dielectric.
4. An IC according to claim 1 , wherein the plurality of polysilicon gates each have an area greater than one μm 2 .
5. An IC according to claim 1 , wherein the high-κ dielectrics and the metal electrodes have compositions and structures such that threshold voltages of the metal gates would be altered by a 5 second heat treatment at 1000° C.
6. An IC according to claim 1 , wherein the plurality of polysilicon gates have dielectric thickness adapted for operation with a gate voltage of 10V or higher.
7. An IC according to claim 2 , wherein:
the embedded flash memory comprises control gate electrodes directly over floating gate electrodes; and
top surfaces of the control gate electrodes are coplanar with the top surfaces of the metal electrodes and the top surfaces of the polysilicon electrodes.
8. An integrated circuit (IC) comprising:
a semiconductor substrate comprising a memory area and a periphery area;
a memory device formed in the memory area;
a high-κ metal gate formed in the periphery area; and
a polysilicon gate formed in the periphery area;
wherein the polysilicon gate has an area that is larger than an area of the high-κ metal gate; and
the polysilicon gate has a top surface that is coplanar with a top surface of the high-κ metal gate.
9. An IC according to claim 8 , wherein the polysilicon gate has an area greater than a design limit for high-κ metal gates.
10. An IC according to claim 8 , wherein:
the semiconductor substrate is implanted with dopants in source and drain regions operatively associated with the high-κ metal gate;
the source and drain regions have physical structures resulting from annealing after the dopants were implanted; and
the high-κ metal gate has a structure that would not be possible if the high-κ metal gate had been subjected to the annealing.
11. An IC according to claim 8 , wherein:
the polysilicon gate comprises a polysilicon electrode, a channel region, and one or more dielectrics spanning from the channel region to the polysilicon electrode; and
each of the one or more dielectrics of the polysilicon gate has a dielectric constant that is lower than that of any high-κ dielectric.
12. An IC according to claim 8 , wherein the polysilicon gate has an area greater than one μm 2 .
13. An IC according to claim 8 , wherein:
the memory device comprises control gates directly over floating gates; and
top surfaces of the control gates are coplanar with the top surfaces of the metal electrodes and the top surfaces of the polysilicon electrodes.
14. A method of forming an integrated circuit (IC) comprising:
providing a semiconductor substrate comprising a memory area and a periphery area, the periphery area comprising a first region and a second region;
forming a gate oxide layer in the first region;
forming a polysilicon layer over the first region and the second region, whereby the polysilicon layer forms over the gate oxide layer;
forming a protective layer over the polysilicon layer;
masking the first region;
with the first region masked, selectively removing the protective layer and the polysilicon layer from the second region;
forming a high-κ dielectric layer over the first region and the second region;
forming a dummy electrode layer over the high-κ dielectric layer;
patterning the dummy electrode layer and the high-κ dielectric layer to form dummy gates in the second region and to remove the dummy electrode layer and the high-κ dielectric layer from the first region;
patterning the protective layer and the polysilicon layer to define polysilicon gates in the first region;
forming spacers adjacent the dummy gates;
filing an area adjacent the spacers;
planarizing the first and second regions;
removing the dummy electrode layer from the dummy gates to form voided areas;
depositing metal over the first and second regions, whereby the metal fills the voided areas to form high-κ metal gates; and
planarizing the first and second regions to remove excess metal;
wherein planarizing the first and second regions to remove excess metal leaves top surfaces of the high-κ metal gates coplanar with top surfaces of the polysilicon gates;
the polysilicon gates have greater areas than the high-κ metal gates; and
a memory device is formed in the memory area.
15. A method according to claim 14 , further comprising forming a hard mask over the dummy electrode layer before patterning the dummy electrode layer and the high-κ dielectric layer to form dummy gates.
16. A method according to claim 14 , further comprising performing a silicide process on the polysilicon gates after planarizing the first and second regions to remove excess metal.
17. A method according to claim 14 , wherein the polysilicon gates each have an area greater than one μm 2 .
18. A method according to claim 14 , wherein the polysilicon gates are operative as high voltage gates.
19. A method according to claim 14 , wherein the memory device is flash memory.
20. A method according to claim 19 , wherein:
the flash memory comprises control gate electrodes directly over floating gate electrodes; and
top surfaces of the control gate electrodes are coplanar with the top surfaces of the high-κ metal gates and the top surfaces of the polysilicon gates.