IP Library › Granted Patent US 11,573,593
Granted Patent B2
US 11,573,593 · App. 15/954,051 · Granted Feb 7, 2023

Level-based droop detection

Inventors: Richard Martin Born (Fort Collins, CO); Stephen Victor Kosonocky (Fort Collins, CO); Miguel Rodriguez (Fort Collins, CO)
Assignee: Advanced Micro Devices, Inc.
G06F1/08G06F1/28G06F1/305H03K5/00006
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,573,593
App. No.
15/954,051
Granted
Feb 7, 2023
Kind
B2
Abstract

A power regulator provides current to a processing unit. A clock distribution network provides a clock signal to the processing unit. A level-based droop detector monitors a voltage of the current provided to the processing unit and provides a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage. The clock distribution network decreases a frequency of a clock signal provided to the processing unit in response to receiving the droop detection signal. The level-based droop detector interrupts the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage. The clock distribution network increases the frequency of the clock signal provided to the processing unit in response to interruption of the droop detection signal.

Claims (50)

1. A method comprising:

in response to a voltage provided to a processing unit falling below a first threshold voltage,

providing a droop detection signal to a synchronization circuit, the synchronization circuit configured to synchronize the droop detection signal with one or more clock signals generated by a clock distribution network and further configured to selectively provide the droop detection signal at different time delays; and

in response to receiving the droop detection signal at the clock distribution network,

decreasing a frequency of a variable rate clock signal provided to the processing unit by the clock distribution network.

2. The method of claim 1 , further comprising:

interrupting the droop detection signal to the clock distribution network in response to the voltage rising above a second threshold voltage different from the first threshold voltage; and

increasing the frequency of the variable rate clock signal provided to the processing unit by the clock distribution network in response to interruption of the droop detection signal.

3. The method of claim 2 , further comprising:

in response to a plurality of droops in the voltage that occurred during different time intervals, providing and interrupting the droop detection signal a plurality of times.

4. The method of claim 3 , wherein durations of the different time intervals range from nanoseconds to milliseconds.

5. The method of claim 1 , further comprising:

providing the variable rate clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and

providing the variable rate clock signal at a second frequency in response to the clock distribution network receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

6. The method of claim 5 , further comprising:

providing the variable rate clock signal at the first frequency in response to interruption of the droop detection signal.

7. The method of claim 6 , further comprising:

in response to the clock distribution network receiving the droop detection signal, increasing a number of oscillations between high and low phases of a phase locked loop that generates the variable rate clock signal; and

decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

8. An apparatus comprising:

a clock distribution network configured to provide a variable rate clock signal to a processing unit;

a level-based droop detector configured to monitor a voltage of a current provided to the processing unit and provide a droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage;

a synchronization circuit configured to provide variable length synchronization of the droop detection signal with one or more variable rate clock signals generated by the clock distribution network and further configured to selectively provide the droop detection signal at different delays; and

wherein the clock distribution network is configured to decrease a frequency of the variable rate clock signal provided to the processing unit in response to receiving the droop detection signal.

9. The apparatus of claim 8 , wherein:

the level-based droop detector is configured to interrupt the droop detection signal that is provided to the clock distribution network in response to the voltage rising above a second threshold voltage different from the first threshold voltage; and

the clock distribution network is configured to increase the frequency of the variable rate clock signal provided to the processing unit in response to interruption of the droop detection signal.

10. The apparatus of claim 9 , wherein the level-based droop detector comprises:

a voltage source configured to generate the first threshold voltage; and

a comparator configured to compare the first threshold voltage generated by the voltage source to the voltage provided to the processing unit, wherein the comparator is configured to generate the droop detection signal based on the comparison.

11. The apparatus of claim 8 , wherein the level-based droop detector is configured to provide an interrupt in the droop detection signal a plurality of times in response to a plurality of droops in the voltage that occurred during different time intervals.

12. The apparatus of claim 11 , wherein durations of the different time intervals range from nanoseconds to milliseconds.

13. The apparatus of claim 8 , wherein the clock distribution network is configured to:

provide the variable rate clock signal at a first frequency prior to the clock distribution network receiving the droop detection signal; and

provide the variable rate clock signal at a second frequency in response to receiving the droop detection signal, wherein the second frequency is lower than the first frequency.

14. The apparatus of claim 13 , wherein the clock distribution network is configured to provide the variable rate clock signal at the first frequency in response to interruption of the droop detection signal.

15. The apparatus of claim 14 , wherein the clock distribution network comprises:

a phase locked loop to provide a fixed rate clock signal; and

a digital frequency synthesizer to provide the variable rate clock signal by modifying a fixed rate clock signal.

16. The apparatus of claim 15 , wherein the digital frequency synthesizer is configured to provide the variable rate clock signal at the second frequency by increasing a number of oscillations between high and low phases of the phase locked loop in response to the clock distribution network receiving the droop detection signal.

17. The apparatus of claim 16 , wherein the digital frequency synthesizer is configured to provide the variable rate clock signal at the first frequency in response to interruption of the droop detection signal by decreasing the number of oscillations between the high and low phases of the phase locked loop in response to interruption of the droop detection signal.

18. An apparatus comprising:

at least one clock distribution network configured to provide a first clock signal to a first clock domain in a first power domain and a second clock signal to a second clock domain in a second power domain;

a first level-based droop detector configured to monitor a voltage to the first power domain and provide a first droop detection signal to the clock distribution network in response to the voltage falling below a first threshold voltage;

a second level-based droop detector configured to monitor a voltage to the second power domain and provide a second droop detection signal to the clock distribution network in response to the voltage falling below a second threshold voltage;

wherein the at least one clock distribution network is configured to decrease a first frequency of the first clock signal provided to the first clock domain in response to receiving the first droop detection signal; and

wherein the at least one clock distribution network is configured to decrease a second frequency of the second clock signal provided to the second clock domain in response to receiving the second droop detection signal.

19. The apparatus of claim 18 , further comprising:

a synchronization network configured to synchronize the first and second clock signals subject to a constraint.

20. The apparatus of claim 19 , wherein the synchronization network is configured to synchronize the first and second clock signal such that the first frequency is less than or equal to the second frequency.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2018
From: BORN, RICHARD MARTIN; KOSONOCKY, STEPHEN VICTOR; RODRIGUEZ, MIGUEL
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 046484/0920 →
Continuity (1)
Related Publication 20190317546A1 · Oct 17, 2019