Circuits and methods for capacitor modulation
In a particular implementation, a circuit comprises: a memory array including a plurality of bit cells, where each of the bit cells are coupled to a respective bit path; a first multiplexer comprising a plurality of column address locations, where each of the plurality of column address locations is coupled to the memory array and corresponds to a respective bit path capacitance; and a variable capacitance circuit coupled to a reference path and configured to substantially match reference path capacitance to each of the respective bit path capacitances.
1. An integrated circuit comprising:
a memory array comprising a plurality of bit cells coupled to respective bit paths, wherein the memory array comprises a magnetic random access memory (MRAM) array, and wherein each of the bit cells comprise magnetic tunnel junction (MTJ) bit cells;
a first multiplexer comprising a plurality of column address locations, wherein each of the plurality of column address locations is coupled to a corresponding bit cell in the memory array, and wherein each of the plurality of column address locations corresponds to a respective bit path capacitance for each of the respective bit paths;
an amplifier circuit coupled to the first multiplexer, wherein the amplifier circuit is configured to sense the column address location corresponding to the bit cell to be read by way of a reference path; and
a variable capacitance circuit coupled to the amplifier circuit by way of the a reference path, wherein the variable capacitance circuit is configured to substantially match a reference path capacitance to each of the respective bit path capacitances by adjusting the reference path capacitance to substantially match bit path capacitance corresponding to the column address location of the bit cell to be read.
2. The integrated circuit of claim 1 , wherein the integrated circuit is configured to adjust the reference path capacitance to align to each of bit path capacitances of the plurality of column address locations.
3. The integrated circuit of claim 1 , wherein each of the column address locations comprises a respective pass-transistor gate configured as a switch of the first multiplexer.
4. The integrated circuit of claim 1 , wherein the variable capacitance circuit comprises a second multiplexer and one or more address dependent variable capacitors, and wherein each of the one or more address dependent variable capacitors is configured to approximately equate to the respective bit path capacitance.
5. The integrated circuit of claim 4 , wherein the second multiplexer comprises a switch, and wherein the switch is coupled to the one or more address dependent variable capacitors.
6. The integrated circuit of claim 4 , wherein each of the one or more address dependent variable capacitors comprises a respective NMOS transistor coupled to a reference capacitor.
7. The integrated circuit of claim 4 , wherein the one or more address dependent variable capacitors comprise at least first and second the one or more address dependent variable capacitors coupled in series.
8. The integrated circuit of claim 1 , further comprising:
a column decoder coupled to each of the one or more address dependent variable capacitors and configured to select one of the plurality of column address locations.
9. The integrated circuit of claim 8 , wherein based on the selection of the column address location, the variable capacitance circuit is configured to adjust the reference path capacitance on the reference path.
10. The integrated circuit of claim 1 , wherein the amplifier circuit is further configured to:
determine a reference capacitance value corresponding to a bit capacitance value.
11. The integrated circuit of claim 1 , wherein the variable capacitance circuit is configured to:
alter the reference capacitor value to substantially equate to the column address location.