Calibration control circuit and storage device comprising the calibration control circuit
A memory device includes a calibration circuit configured to perform a ZQ calibration operation according to a calibration command signal and a calibration power voltage, and a calibration control circuit configured to determine the calibration command signal based on a comparison result obtained by comparing the calibration power voltage level with at least one reference voltage level.
1. A memory device, comprising:
a calibration circuit configured to perform a ZQ calibration operation according to a calibration command signal and a calibration power voltage; and
a calibration control circuit configured to determine the calibration command signal based on a comparison result obtained by comparing a level of the calibration power voltage with a level of at least one reference voltage.
2. The memory device of claim 1 , wherein the calibration control circuit is configured to determine a logic state of the calibration command signal based on the comparison result obtained by comparing the level of the calibration power voltage with the level of the at least one reference voltage for a certain period of time.
3. The memory device of claim 2 , wherein the calibration control circuit further comprises:
a counter configured to output a signal for determining a logic state of the calibration command signal by receiving the comparison result in every counting timing.
4. The memory device of claim 3 , wherein the counter is configured to output the calibration command signal having a high logic level when the comparison result of the comparing indicates that the level of the calibration power voltage is equal to or greater than the level of the at least one reference voltage and the comparison result is received in at least one counting timing.
5. The memory device of claim 3 , wherein the counter is configured to output the calibration command signal having a low logic level when the comparison result indicates that the level of the calibration power voltage is lower than the level of the at least one reference voltage and the comparison result is received in a counting timing in a number that is equal to or greater than a certain consecutive number of times.
6. The memory device of claim 1 , wherein the calibration control circuit is configured to compare the level of the calibration power voltage with different reference voltage levels according to a logic state of the calibration command signal.
7. The memory device of claim 6 , wherein the calibration control circuit is configured to compare the level of the calibration power voltage with one of the different reference voltage levels when the calibration command signal is a logic high signal, and transition the calibration command signal to a low logic level when the level of the calibration power voltage is less than the one of the different reference voltage levels.
8. The memory device of claim 6 , wherein the calibration control circuit is configured to compare the level of the calibration power voltage with one of the different reference voltage levels when the calibration command signal is a logic low signal, and transition the calibration command signal to a high logic level when the level of the calibration power voltage is equal to or higher than the one of the different reference voltage levels.
9. A calibration control circuit, comprising:
a comparator configured to obtain a comparison result by comparing a calibration power voltage, which is input to a calibration circuit configured to perform a ZQ calibration operation, with at least one reference voltage; and
a command signal output unit configured to output a calibration command signal used to determine whether the calibration circuit performs the ZQ calibration operation based on the comparison result.
10. The calibration control circuit of claim 9 , wherein the command signal output unit comprises:
a counter configured to receive the comparison result from the comparator in every counting timing and output the calibration command signal based on the comparison result for a certain period of time.
11. The calibration control circuit of claim 10 , wherein the counter is configured to output the calibration command signal having a high logic level when the comparison result indicates that a level of the calibration power voltage is equal to or higher than a level of the at least one reference voltage and the comparison result is received in at least one counting timing.
12. The calibration control circuit of claim 10 , wherein the counter is configured to output the calibration command signal having a low logic level when the comparison result indicates that a level of the calibration power voltage is lower than a level of the at least one reference voltage and the comparison result is received in a number that is equal to or greater than a certain consecutive number of times.
13. The calibration control circuit of claim 9 , wherein the comparator is configured to compare the calibration power voltage with different reference voltages according to a logic state of the calibration command signal.
14. The calibration control circuit of claim 13 , wherein, when the calibration command signal is a logic high signal, the calibration control circuit is configured to transition the calibration command signal to a low logic level when the calibration power voltage is lower than the at least one reference voltage compared to the calibration power voltage.
15. The calibration control circuit of claim 13 , wherein, when the calibration command signal is a logic low signal, the calibration control circuit is configured to transition the calibration command signal to high logic level when the calibration power voltage is equal to or higher than the at least one reference voltage compared to the calibration power voltage.
16. An operation method of a memory device, the method comprising:
comparing a calibration power voltage, which is input to a calibration circuit configured to perform a ZQ calibration operation, with at least one reference voltage; and
determining a logic state of a calibration command signal used to determine whether the calibration circuit performs the ZQ calibration operation based on a comparison result obtained by comparing the calibration power voltage with the at least one reference voltage.
17. The operation method of claim 16 , wherein the logic state of the calibration command signal is determined for a certain period of time by receiving the comparison result in every counting timing of a counter.
18. The operation method of claim 17 , wherein determining the logic state of the calibration command signal comprises:
outputting the calibration command signal having a low logic level when the comparison result indicates that the calibration power voltage is lower than the at least one reference voltage and the comparison result is received in a number that is equal to or greater than a certain consecutive number of times.
19. The operation method of claim 16 , wherein the comparing comprises comparing different reference voltages with the calibration power voltage according to the logic state of the calibration command signal.
20. The operation method of claim 19 , wherein determining the logic state of the calibration command signal comprises:
comparing the calibration power voltage with a first reference voltage when the calibration command signal is a logic high signal;
transitioning the calibration command signal to a low logic level when the calibration power voltage is lower than the first reference voltage;
comparing the calibration power voltage with a second reference voltage when the calibration command signal is a logic low signal; and
transitioning the calibration command signal to a high logic level when the calibration power voltage is equal to or higher than the second reference voltage.