Display device with gate conductive layer forming wire pad in pad area and method of fabricating the same

1. A display device comprising:

a substrate including a display area and a pad area;

a gate conductive layer disposed on the substrate, the gate conductive layer comprising:

a gate conductive metal layer and a gate capping layer that is disposed on the gate conductive metal layer; and

the gate conductive layer forms a gate electrode disposed in the display area and

a wire pad disposed in the pad area;

an interlayer insulating film disposed on the gate conductive layer and covering the gate electrode, wherein the wire pad is exposed by a pad opening;

a data conductive layer disposed on the interlayer insulating film in the display area, the data conductive layer including source and drain electrodes;

a passivation layer disposed on the data conductive layer and covering the source and drain electrodes;

a via layer disposed on the passivation layer; and

a pixel electrode disposed on the via layer, the pixel electrode is connected to the source electrode through a contact hole that penetrates the via layer and the passivation layer,

wherein

the via layer includes a first region overlapping with the pixel electrode in the display area and a second region not overlapping with the pixel electrode in the display area and having a smaller height than a height of the first region.

2. The display device of claim 1 , wherein:

the pad opening is formed by the interlayer insulating film and the via layer; and

the interlayer insulating film and the via layer form aligned inner sidewalls of the pad opening.

3. The display device of claim 2 , wherein the passivation layer is not disposed in the pad area.

4. The display device of claim 3 , wherein the via layer is disposed directly on the interlayer insulating film in the pad area.

5. The display device of claim 2 , wherein:

the via layer further includes a third region which is disposed in the pad area; and

the third region has a smaller height than a height of the second region.

6. The display device of claim 5 , wherein:

the interlayer insulating film includes a first portion disposed in the display area and a second portion disposed in the pad area and having a smaller thickness than a thickness of the first portion; and

the second portion overlaps with the third region of the via layer.

7. The display device of claim 1 , wherein:

the pad opening is formed by the interlayer insulating film and the passivation layer; and

the interlayer insulating film and the passivation layer form aligned inner sidewalls of the pad opening.

8. The display device of claim 7 , wherein the via layer is not disposed in the pad area.

9. The display device of claim 7 , wherein the passivation layer includes a third portion that is disposed in the display area and a fourth portion which is disposed in the pad area and has a smaller thickness than a thickness of the third portion.

10. The display device of claim 1 , wherein:

a pixel-defining film is disposed on the pixel electrode and the pixel-defining film fills the second region of the via layer.

11. The display device of claim 1 , wherein the gate capping layer includes at least one selected from a zinc indium oxide (ZIO) film, an indium zinc oxide (IZO) film, an indium tin oxide (ITO) film, and a titanium (Ti)/molybdenum (Mo)/indium tin oxide (ITO) film.

12. The display device of claim 11 , wherein the gate conductive metal layer includes a gate main metal layer that contacts the gate capping layer from below the gate capping layer, the gate main metal layer including copper (Cu).

13. A method of fabricating a display device, comprising:

forming a substrate including a display area and a pad area;

forming a gate conductive layer on the substrate, the gate conductive layer including a gate conductive metal layer and a gate capping layer deposited on the gate conductive metal layer, the gate conductive layer forming a gate electrode disposed in the display area, and a wire pad disposed in the pad area;

forming an interlayer insulating film on the gate conductive layer;

forming a data conductive layer on the interlayer insulating film, the data conductive layer including source and drain electrodes that are disposed in the display area;

forming a passivation layer on the data conductive layer;

forming a via layer on the passivation layer, the via layer including a first opening that overlaps with the source electrode in the display area and a second opening that overlaps with the wire pad in the pad area;

forming a first material layer for forming a pixel electrode on the via layer, forming a first mask pattern on the first material layer, and etching the first material layer using the first mask pattern; and

exposing the wire pad by etching the interlayer insulating film, which overlaps with the wire pad, with a remaining portion of the first mask pattern.

14. The method of claim 13 , wherein the etching the interlayer insulating film with the remaining portion of the first mask pattern is performed by an entire-surface etching process.

15. The method of claim 14 , wherein a portion of the via layer not covered by the first mask pattern is etched by the entire-surface etching process and the via layer is divided into a first region overlapping with the pixel electrode and a second region not overlapping with the pixel electrode and having a smaller height than a height of the first region.

16. The method of claim 13 , wherein the forming of the passivation layer comprises:

forming a second material layer on the data conductive layer;

forming a second mask pattern on the second material layer to expose the pad area and a portion of the second material layer that overlaps with the source electrode; and

etching the passivation layer using the second mask pattern.

17. The method of claim 16 , wherein during the etching of the passivation layer, a portion of the interlayer insulating film in the pad area is etched to divide the interlayer insulating film into a first portion disposed in the display area and a second portion disposed in the pad area and having a smaller thickness than a thickness of the first portion.

18. The method of claim 13 , further comprising:

forming the via layer on a portion of the passivation layer that is not etched by performing an entire-surface etching to remove a portion of the passivation layer exposed by the second opening of the via layer.

19. The method of claim 13 , wherein the gate capping layer includes at least one selected from zinc indium oxide (ZIO) film, an indium zinc oxide (IZO) film, an indium tin oxide (ITO) film, and a titanium (Ti)/molybdenum (Mo)/indium tin oxide (ITO) film.

20. The method of claim 19 , wherein the gate conductive metal layer includes a gate main metal layer that is in contact with the gate capping layer from below the gate capping layer and includes copper (Cu).

21. A display device comprising:

a substrate including a display area and a pad area;

a gate conductive layer disposed on the substrate, the gate conductive layer comprising:

a gate conductive metal layer and a gate capping layer that is disposed above the gate conductive metal layer; and

the gate conductive layer forms a gate electrode disposed in the display area and a wire pad disposed in the pad area;

an interlayer insulating film disposed on the gate conductive layer and covering the gate electrode; and

the gate capping layer of the wire pad is exposed by a pad opening and the gate capping layer is configured to be a contact electrode for the wire pad.