IP Library Granted Patent US 11,575,039
Granted Patent B2
US 11,575,039 · App. 17/012,160 · Granted Feb 7, 2023

Semiconductor device

Inventors: Tatsuya Shiraishi (Nonoichi Ishikawa, JP); Masaharu Shimabayashi (Kanazawa Ishikawa, JP)
Assignees: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
H01L29/7813H01L29/401H01L29/42364H01L29/511H01L21/0217H01L21/02271H01L21/28202H01L29/16H01L29/407H01L29/518
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Quick Facts
Patent No.
US 11,575,039
App. No.
17/012,160
Granted
Feb 7, 2023
Kind
B2
Abstract

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide; a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride; a third semiconductor region of first conductivity type provided on the first semiconductor region; a fourth semiconductor region of first conductivity type provided on the second semiconductor region; an interlayer insulating film provided on the third electrode; and a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.

Claims (34)

1. A semiconductor device comprising:

a first electrode;

a first semiconductor layer of first conductivity type provided on the first electrode;

a second semiconductor layer of first conductivity type provided on the first semiconductor layer;

a first semiconductor region of second conductivity type provided on the second semiconductor layer;

a second semiconductor region of second conductivity type provided on the second semiconductor layer;

a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide;

a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon;

a third electrode provided above the second electrode, the third electrode facing the first semiconductor region and the second semiconductor region via a second insulating film containing silicon oxide;

a third insulating film provided between the second electrode and the third electrode, the third insulating film containing silicon nitride;

a third semiconductor region of first conductivity type provided on the first semiconductor region;

a fourth semiconductor region of first conductivity type provided on the second semiconductor region;

an interlayer insulating film provided on the third electrode; and

a fourth electrode provided on the interlayer insulating film, the fourth electrode being electrically connected to the third semiconductor region and the fourth semiconductor region.

2. The semiconductor device according to claim 1 , wherein the third electrode has:

a first portion provided between the second electrode and the interlayer insulating film;

a second portion provided between the second electrode and the first semiconductor region, the second portion being provided below the first portion, the second portion being electrically connected to the first portion; and

a third portion provided between the second electrode and the second semiconductor region, the third portion being provided below the first portion, the third portion being electrically connected to the first portion.

3. The semiconductor device according to claim 2 , wherein the third electrode has an inverted u shape formed with the first portion, the second portion, and the third portion.

4. The semiconductor device according to claim 2 , wherein the third insulating film is provided on a lower surface of the first portion, an inner surface of the second portion, and an inner surface of the third portion.

5. The semiconductor device according to claim 4 , wherein the third insulating film is further provided between the first portion and the first semiconductor region and between the second portion and the second semiconductor region.

6. The semiconductor device according to claim 5 , wherein the third insulating film has a film thickness of 50 nm or less.

7. The semiconductor device according to claim 1 , further comprising a fourth insulating film provided between the third electrode and the third insulating film, the fourth insulating film containing silicon oxide.

8. The semiconductor device according to claim 7 , wherein the third electrode has:

a first portion provided between the second electrode and the interlayer insulating film;

a second portion provided between the second electrode and the first semiconductor region, the second portion being provided below the first portion, the second portion being electrically connected to the first portion; and

a third portion provided between the second electrode and the second semiconductor region, the third portion being provided below the first portion, the third portion being electrically connected to the first portion,

the third insulating film is provided on a lower surface of the first portion, an inner surface of the second portion, and an inner surface of the third portion, and

the fourth insulating film is provided between the third insulating film provided on a lower surface of the first portion and the first portion, between the third insulating film provided on an inner surface of the second portion and the second portion, and between the third insulating film provided on an inner surface of the third portion and the third portion.

9. The semiconductor device according to claim 8 , wherein

the third insulating film is further provided between the first portion and the first semiconductor region and between the second portion and the second semiconductor region, and

the fourth insulating film is provided between the first semiconductor region and the third insulating film provided between the first portion and the first semiconductor region, and between the second semiconductor region and the third insulating film provided between the second portion and the second semiconductor region.

10. The semiconductor device according to claim 1 , wherein the third insulating film has a film thickness of 10 nm or more.

11. The semiconductor device according to claim 1 , wherein the polysilicon contains impurities of conductivity type at a concentration of 1×10 19 atoms/cm 3 or more and 1×10 21 atoms/cm 3 or less.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 30, 2020
From: SHIRAISHI, TATSUYA; SHIMABAYASHI, MASAHARU
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 054488/0143 →
Priority Claims (1)
JP JP2020-050006 · Mar 19, 2020 · national
Continuity (1)
Related Publication 20210296490A1 · Sep 23, 2021