Multi-gate semiconductor device and method for forming the same
A method for forming a multi-gate semiconductor device includes forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate, forming a dummy gate structure across the fin structure, forming a first spacer alongside the dummy gate structure, removing a first portion of the first spacer to expose the dummy gate structure, forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer, removing the dummy gate structure to expose a sidewall of the second spacer, removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure, and forming a gate conductive structure to wrap around the plurality of nanostructures. The gate conductive structure is in contact with the sidewall of the second spacer.
1. A method for forming a multi-gate semiconductor device, comprising:
forming a fin structure including alternating stacked first semiconductor layers and second semiconductor layers over a substrate;
forming a dummy gate structure across the fin structure;
forming a first spacer alongside the dummy gate structure;
removing a first portion of the first spacer to expose the dummy gate structure;
forming a second spacer between a second portion of first spacer and the dummy gate structure after removing the first portion of the first spacer;
removing the dummy gate structure to expose a sidewall of the second spacer;
removing the first semiconductor layers of the fin structure to form a plurality of nanostructures from the second semiconductor layers of the fin structure; and
forming a gate conductive structure to wrap around the plurality of nanostructures, wherein the gate conductive structure is in contact with the sidewall of the second spacer.
2. The method of claim 1 , wherein the first spacer is made of an insulating material and the second spacer is made of a conductive material.
3. The method of claim 1 , further comprising:
forming a barrier layer to cover the sidewall of the second spacer, wherein the plurality of nanostructures is exposed from the barrier layer;
forming a gate dielectric layer to wrap around the plurality of nanostructures; and
removing the barrier layer.
4. The method of claim 1 , wherein forming the gate conductive structure comprising:
forming a barrier metal layer to wrap around the plurality of nanostructures and along the sidewall of the second spacer;
forming a work functional metal layer over the barrier metal layer; and
forming a gap-filling layer over the work functional metal layer.
5. A method for forming a multi-gate semiconductor device, comprising:
forming a dummy gate structure over a channel region of a fin structure;
forming a first insulating spacer along the dummy gate structure;
forming a dielectric structure over a source/drain region of the fin structure;
removing the first insulating spacer to form a first spacer trench between the dielectric structure and the dummy gate structure;
filling a conductive spacer into the first spacer trench;
removing the dummy gate structure to expose a sidewall of the conductive spacer and the channel region of the fin structure;
patterning the channel region of the fin structure to form a plurality of nanostructures;
forming a gate dielectric layer around the nanostructures; and
forming a gate conductive structure over the gate dielectric layer.
6. The method of claim 5 , wherein the gate conductive structure is in contact with the sidewall of the conductive spacer.
7. The method of claim 5 , wherein the conductive spacer includes metal or metal nitride.
8. The method of claim 5 , further comprising:
forming a second insulating spacer along the first insulating spacer, wherein the second insulating spacer is made of a different material than the first insulating spacer, and the first spacer trench is formed between the second insulating spacer and the dummy gate structure.
9. The method of claim 8 , further comprising:
removing the second insulating spacer to form a second spacer trench after forming the gate conductive structure; and
sealing the second spacer trench to form an air spacer.
10. The method of claim 5 , further comprising:
alternatingly stacking first semiconductor layers and second semiconductor layers over a substrate; and
patterning the first semiconductor layers and the second semiconductor layers into the fin structure.
11. The method of claim 10 , further comprising:
removing portions of the first semiconductor layers of the fin structure in the source/drain region to form a plurality of notches;
forming a plurality of inner spacers in the plurality of notches.
12. A method for forming a multi-gate semiconductor device, comprising:
providing a substrate comprising at least a fin structure and a dummy gate structure over the fin structure and the substrate;
disposing an insulating spacer over sidewalls of the dummy gate structure, wherein portions of the fin structure are exposed from the dummy gate structure and the insulating spacer;
forming a source/drain region in the portions of the fin structure exposed from the dummy gate structure and the insulating spacer;
disposing a dielectric structure over the substrate;
disposing a conductive spacer over the sidewalls of the dummy gate structure;
removing the dummy gate structure to form a gate trench in the dielectric structure, wherein the conductive spacer is exposed from sidewalls of the gate trench;
disposing at least a gate dielectric layer over a bottom of the gate trench after removing the dummy gate structure; and
disposing a gate conductive structure in the gate trench, wherein sidewalls of the gate conductive structure are in contact with the conductive spacer.
13. The method of claim 12 , wherein the forming the insulating spacer over the sidewalls of the dummy gate structure further comprises:
disposing a first spacer over the sidewalls of the dummy gate structure; and
disposing a second spacer over the first spacer.
14. The method of claim 13 , wherein the first spacer comprises a first insulating material and the second spacer comprises a second insulating material, and the first insulating material is different from the second insulating material.
15. The method of claim 13 , wherein the disposing of the conductive spacer further comprises:
removing the first spacer to form a first spacer trench over the substrate; and
disposing the conductive spacer in the first spacer trench.
16. The method of claim 15 , wherein the conductive spacer is disposed between the second spacer and the gate conductive structure.
17. The method of claim 15 , further comprising:
removing the second spacer to form a second spacer trench over the substrate; and
sealing the second space trench to form an air spacer.
18. The method of claim 12 , further comprising removing portions of the fin structure to form a plurality of nanostructures exposed through the gate trench.
19. The method of claim 18 , wherein the forming the gate dielectric layer over the bottom of the gate trench further comprises:
disposing a barrier layer over the sidewalls of the gate trench, wherein the plurality of nanostructures is exposed from the barrier layer;
disposing the gate dielectric layer over the plurality of nanostructures exposed from the barrier layer; and
removing the barrier layer to expose the sidewalls of the gate trench.
20. The method of claim 19 , wherein the barrier layer includes a head group having organosulfur compound.