Variable resistance memory device
A variable resistance memory device includes a variable resistance layer, a first conductive element, and a second conductive element. The variable resistance layer includes a first layer and a second layer. The first layer is formed of a first material. The second layer is on the first layer and formed of a second material having a density different from a density of the first material. The first conductive element and a second conductive element are located on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer. The current path is in a direction perpendicular to a direction in which the first layer and the second layer are stacked.
1. A variable resistance memory device comprising:
a variable resistance layer including a first layer, a second layer on the first layer, and a third layer on the second layer,
the first layer formed of a first material,
the second layer formed of a second material,
the third layer formed of a third material; and
a first conductive element and a second conductive element on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked, wherein
the second layer is between the first layer and the third layer,
the third layer is between the second layer and each of the first conductive element and the second conductive element,
a density of the second material is higher than a density of the first material,
a density of the third material is lower than the density of the second material.
2. The variable resistance memory device of claim 1 ,
the first material and the third material are a same one of HfO 2 , Gd 2 O 3 , NiO, and WO 3 , and
the second material is one of TiO 2 , MnO 2 , ZrO 2 , SiO 2 , Cr 2 O 3 , La 2 O 3 , SrO, CaO, BeO, MoO 3 ,
provided that the first material and the second material have a same valence.
3. The variable resistance memory device of claim 1 , wherein a density difference between the first material and the second material is greater than 1 g/cm 3 and less than 8 g/cm 3 .
4. The variable resistance memory device of claim 1 , wherein a density difference between the second material and the third material is greater than 1 g/cm 3 and less than 8 g/cm 3 .
5. The variable resistance memory device of claim 4 , wherein the first material and the third material are a same material.
6. The variable resistance memory device of claim 4 , wherein
a thickness of the second layer is less than a thickness of the first layer, and
the thickness of the second layer is less than a thickness of the third layer.
7. The variable resistance memory device of claim 1 , wherein each of the first material and the second material is an oxide having a bandgap energy of 2 eV or more.
8. The variable resistance memory device of claim 1 , wherein each of the first material and the second material independently is any one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , and MnO 2 .
9. The variable resistance memory device of claim 1 , wherein
the first material and the second material have a same valence, and
a density difference between the first material and the second material is greater than 1.5 g/cm 3 .
10. A variable resistance memory device comprising:
an insulating layer;
a variable resistance layer on the insulating layer, the variable resistance layer including a first layer, a second layer on the first layer, and a third layer on the second layer,
the first layer formed of a first material, the second layer formed of a second material, the third layer formed of a third material;
a channel layer on the variable resistance layer;
a gate insulating layer on the channel layer; and
a plurality of gate electrodes spaced apart from one another on the gate insulating layer, wherein
the first conductive element and the second conductive element are two of the plurality of gate electrodes,
the second layer is between the first layer and the third layer,
the third layer is between the second layer and the plurality of gate electrodes,
a density of the second material is higher than a density of the first material, and
a density of the third material is lower than the density of the second material.
11. The variable resistance memory device of claim 10 , wherein
the first material and the third material are a same one of HfO 2 , Gd 2 O 3 , NiO, and WO 3 , and
the second material is one of TiO 2 , MnO 2 , ZrO 2 , SiO 2 , Cr 2 O 3 , La 2 O 3 , SrO, CaO, BeO, MoO 3 ,
provided that the first material and the second material have a same valence.
12. The variable resistance memory device of claim 10 , wherein a density difference between the first material and the second material is greater than 1 g/cm 3 and less than 8 g/cm 3 .
13. The variable resistance memory device of claim 10 , wherein a thickness of each of the first layer, the second layer, and the third layer is equal to or less than 10 nm.
14. The variable resistance memory device of claim 13 , wherein the second layer has a thickness equal to or less than 2 nm.
15. The variable resistance memory device of claim 13 , wherein the third layer contacts the channel layer and has a thickness equal to or greater than 5 nm.
16. The variable resistance memory device of claim 10 , wherein a density difference between the second material and the third material is greater than 1 g/cm 3 and less than 8 g/cm 3 .
17. The variable resistance memory device of claim 10 , wherein the first material and the third material are a same material.
18. The variable resistance memory device of claim 10 , wherein each of the first material and the second material is an oxide having a bandgap energy of 2 eV or more.
19. The variable resistance memory device of claim 10 , wherein each of the first material and the second material independently is any one of Rb 2 O, TiO 2 , BaO, ZrO 2 , CaO, HfO 2 , SrO, Sc 2 O 3 , MgO, Li 2 O, Al 2 O 3 , SiO 2 , BeO, Nb 2 O 5 , NiO, Ta 2 O 5 , WO 3 , V 2 O 5 , La 2 O 3 , Gd 2 O 3 , CuO, MoO 3 , Cr 2 O 3 , and MnO 2 .
20. A variable resistance memory device comprising:
a variable resistance layer including a first layer and second layer,
the first layer formed of a first material,
the second layer on the first layer, the second layer formed of a second material, and
a density of the first material being higher than a density of the second material; and
a first conductive element and a second conductive element on the variable resistance layer and spaced apart from each other in order to form a current path in the variable resistance layer in a direction perpendicular to a direction in which the first layer and the second layer are stacked, wherein
the first material is HfO 2 and the second material is MnO 2 , ZrO 2 , SiO 2 , or Cr 2 O 3 ,
the first material is Gd 2 O 3 and the second material is Cr 2 O 3 or La 2 O 3 ,
the first material is NiO and the second material is SrO, CaO, or BeO, or
the first material is WO 3 and the second material is MoO 3 .
21. The variable resistance memory device of claim 20 , wherein
the first material is HfO 2 , and
the second material is TiO 2 , MnO 2 , ZrO 2 , SiO 2 , or Cr 2 O 3 .
22. The variable resistance memory device of claim 20 , wherein
the first material is Gd 2 O 3 , and
the second material is Cr 2 O 3 or La 2 O 3 .
23. The variable resistance memory device of claim 20 , wherein
the first material is NiO, and
the second material is SrO, CaO, or BeO.
24. The variable resistance memory device of claim 14 , wherein
the first material is WO 3 , and
the second material is MoO 3 .
25. A variable resistance memory device comprising:
an insulating layer;
the variable resistance memory device of claim 20 on the insulating layer;
a channel layer on the variable resistance layer;
a gate insulating layer on the channel layer; and
a plurality of gate electrodes spaced apart from another on the gate insulating layer, wherein
the first conductive element and the second conductive element are two of the plurality of gate electrodes.