IP Library Granted Patent US 11,575,495
Granted Patent B2
US 11,575,495 · App. 17/210,347 · Granted Feb 7, 2023

One-step timestamping in network devices

Inventors: Nitzan Dror (Ramot Hashavim, IL); Lenin Patra (Dublin, CA); Jeng-Jong Chen (Santa Clara, CA)
Assignee: Marvell Israel (M.I.S.L) Ltd.
H04L7/0016
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Quick Facts
Patent No.
US 11,575,495
App. No.
17/210,347
Granted
Feb 7, 2023
Kind
B2
Abstract

A media access control (MAC) processor of a network device receives a timing packet to be transmitted by the network device. The MAC processor generates one or more indicators to be used by a PHY device of the network device for embedding timing information into the timing packet. The one or more indicators include at least an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded, an indicator of a location of a field in the timing packet at which the timing information is to be embedded, and an indicator of whether timing information in the timing packet needs to be updated. The MAC processor transfers the timing packet and the one or more indicators to the PHY device for further processing of the timing packet and subsequent transmission of the timing packet from the network device.

Claims (62)

1. A method for processing timing packets for synchronizing network devices in a network device, the method comprising:

receiving, at a media access control (MAC) processor of the network device, a timing packet to be transmitted by the network device;

performing initial processing of the timing packet by the MAC processor, including generating one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device; and

transferring i) the timing packet and ii) the one or more indicators from the MAC processor to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

2. The method of claim 1 , further comprising

generating, by the MAC processor, a control header to include the one or more indicators generated for the timing packet, and

inserting, by the MAC processor, the control header into the timing packet prior to transferring the timing packet to the PHY device.

3. The method of claim 2 , further comprising

generating, by the MAC processor, a PHY tag to be included in the control header,

generating, by the MAC processor, the control header to include a PHY tag in an extension field of the control header, and

inserting the control header at a predetermined location within the timing packet prior to transferring the timing packet to the PHY device.

4. The method of claim 3 , wherein inserting the control header at the predetermined location in the timing packet comprises replacing, with the control header, a preamble at a beginning of the timing packet.

5. The method of claim 4 , wherein generating the PHY tag includes generating the PHY tag to include one or more of i) an offset indicator field set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field set to indicate whether a checksum update is needed for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field indicates to the PHY device whether a wraparound of a correction field value is to be accounted for by the PHY device.

6. The method of claim 1 , wherein receiving the timing packet comprises receiving one of i) a timing packet generated by a host processor of the network device or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device, and wherein the timing information to be embedded into the timing packet indicates one of i) a time corresponding to transmission of the timing packet from the network device or ii) a residence time of the timing packet in the network device.

7. A network device configured to operate in a network, the network device comprising:

a media access control (MAC) processor configured to

receive a timing packet to be transmitted by the network device,

generate one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device; and

transfer i) the timing packet and ii) the one or more indicators to the PHY device for further processing of the timing packet based on the one or more indicators and subsequent transmission of the timing packet from the network device.

8. The network device of claim 7 , wherein the MAC processor is further configured to

generate a control header to include the one or more indicators, and

insert the control header into the timing packet prior to transferring the timing packet to the PHY device.

9. The network device of claim 8 , wherein the MAC processor is further configured to

generate a PHY tag to be included in the control header,

generate the control header to include the PHY tag in an extension field of the control header, and

insert the control header at a predetermined location within the timing packet prior to transferring the timing packet to the PHY device.

10. The network device of claim 9 , wherein the MAC processor is configured to replace, with the control header, a preamble at a beginning of the timing packet.

11. The network device of claim 8 , wherein the MAC processor is configured to generate the PHY tag to include one or more of i) an offset indicator field set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet, ii) a checksum update indicator field set to indicate whether a checksum update is needed for the timing packet, and iii) a timestamp least significant bit (LSB) field, wherein the timestamp LSB field is set to indicate to the PHY device whether a wraparound of a correction field value is to be accounted for by the PHY device.

12. The network device of claim 7 , wherein

the timing packet is one of i) a timing packet generated by a host processor of the network device or ii) receiving a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device.

13. The network device of claim 7 , wherein the timing information to be embedded in the timing packet indicates one of i) a time corresponding to transmission of the timing packet from the network device or ii) a residence time of the timing packet in the network device.

14. A network device configured to operate in a network, the network device comprising:

a media access control (MAC) processor coupled to a physical layer (PHY) device, wherein the MAC processor is configured to

receive a timing packet to be transmitted by the network device,

generate one or more indicators of one or more parameters to be used by a PHY device of the network device for embedding timing information into the timing packet, the one or more indicators including at least i) an indicator indicating that the timing packet is a type of packet into which timing information is to be embedded by the PHY device, ii) an indicator of a location of a field in the timing packet at which the timing information is to be embedded into the timing packet by the PHY device, and iii) an indicator of whether timing information in the timing packet needs to be updated by the PHY device; and

transfer i) the timing packet and ii) the one or more indicators to the PHY device; wherein

the PHY device is configured to

receive i) the timing packet from the MAC processor and ii) the one or more indicators from the MAC processor;

embed, based on the one or more indicators, timing information into the timing packet; and

forward the timing packet to one or more network ports of the network device for transmission of the timing packet from the network device.

15. The network device of claim 14 , wherein

the timing packet is one of i) a timing packet generated by a host processor of the network device or ii) a timing packet previously received by the network device, the timing packet previously received by the network device including a correction field for indicating a residence time of the timing packet in the network device, and

the timing information to be embedded in the timing packet indicates one of i) a time corresponding to transmission of the timing packet from the network device or ii) a residence time of the timing packet in the network device.

16. The network device of claim 14 , wherein

the MAC processor is configured to receive a timing packet that includes i) a timestamp and ii) a value of a correction field generated based on a clock maintained by a host processor of the network device, and

the PHY device is configured to embed the timing information into the timing packet at least by updating the value of the correction field based on a clock maintained by the PHY device of the network device.

17. The network device of claim 16 , wherein

the MAC processor is configured to

generate a PHY tag to include an offset indicator field set to indicate an offset of a correction field in the timing packet relative to a delimiter field of the timing packet,

generate a control header to include the PHY tag in an extension field of the control header, and

replace, with the control header, a preamble at a beginning of the timing packet prior to transferring the timing packet to the PHY device, and

the PHY device is configured to update the correction field at the offset indicated by the offset indicator field and without parsing the timing packet to locate the correction field within the timing packet.

18. The network device of claim 17 , wherein

the MAC processor is configured to generate the PHY tag to further include a checksum update indicator field set to indicate whether a checksum update is needed for the timing packet, and

the PHY device is configured to

determine, based on the checksum update indicator field, whether a checksum update is needed for the timing packet, and

in response to determining that a checksum update is needed for the timing packet, perform an incremental update of a checksum trailer field in the timing packet.

19. The network device of claim 17 , wherein

the MAC processor is configured to generate the PHY tag to further include a timestamp least significant bit (LSB) field, wherein the timestamp LSP field indicates whether a wraparound of a correction field value is to be accounted for by the PHY device, and

the PHY device is configured to

determine, based on the timestamp LSB field, whether wraparound of the correction field value is to be accounted for by the PHY device, and

in response to determining that wraparound of the correction field value is to be accounted for by the PHY device, update the correction field to account for wraparound in the correction field.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2021
From: DROR, NITZAN
To: MARVELL ISRAEL (M.I.S.L) LTD
Reel/Frame 057235/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2021
From: PATRA, LENIN; CHEN, JENG-JONG
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 057235/0238 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2021
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL ISRAEL (M.I.S.L) LTD.
Reel/Frame 057235/0287 →
Continuity (2)
Provisional Application 62993524 · Mar 23, 2020
Related Publication 20210297230A1 · Sep 23, 2021
Cited By (2)
US 12,316,726 US 12,647,203