IP Library Granted Patent US 11,575,847
Granted Patent B2
US 11,575,847 · App. 17/185,539 · Granted Feb 7, 2023

Solid-state imaging device, method of driving the same, and electronic apparatus

Inventor: Fumihiko Koga (Kanagawa, JP)
Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
H04N5/3575H01L27/1464H01L27/14612H01L27/14636H01L27/14645H01L27/14647H01L27/14665H01L27/307H04N5/363H04N5/365H04N5/367H04N5/369H04N5/374H04N5/37455H04N5/37457H04N9/045H01L27/14621H01L27/14627H04N9/04557
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Quick Facts
Patent No.
US 11,575,847
App. No.
17/185,539
Granted
Feb 7, 2023
Kind
B2
Abstract

The present technology relates to a solid-state imaging device that can improve imaging quality by reducing variation in the voltage of a charge retention unit, a method of driving the solid-state imaging device, and an electronic apparatus. A first photoelectric conversion unit generates and accumulates signal charge by receiving light that has entered a pixel, and photoelectrically converting the light. A first charge retention unit retains the generated signal charge. A first output transistor outputs the signal charge in the first charge retention unit as a pixel signal, when the pixel is selected by the first select transistor. A first voltage control transistor controls the voltage of the output end of the first output transistor. The present technology can be applied to pixels in solid-state imaging devices, for example.

Claims (52)

1. A light detecting device, comprising:

a pixel, the pixel comprising:

a first photoelectric conversion element;

a first diffusion layer electrically coupled to the first photoelectric conversion element;

a first transistor, a gate of the first transistor being electrically coupled to the first diffusion layer;

a second transistor, one of a source or a drain of the second transistor being electrically coupled to one of a source or a drain of the first transistor; and

a third transistor, one of a source or a drain of the third transistor being electrically coupled to the one of the source or the drain of the first transistor and being electrically coupled to the one of the source or the drain of the second transistor, wherein the first transistor and the third transistor have a same channel type, and

wherein the other of the source or the drain of the first transistor and the other of the source or the drain of the third transistor are electrically coupled to a node that receives a power supply voltage so that, when the node is coupled to the power supply voltage, a voltage of the other of the source or the drain of the first transistor is equal to a voltage of the other of the source or the drain of the third transistor.

2. The light detecting device according to claim 1 , wherein the first photoelectric conversion element is configured to generate and accumulate signal charge by receiving light having entered the pixel and photoelectrically converting the light.

3. The light detecting device according to claim 2 , wherein the signal charge generated by the first photoelectric conversion element comprises holes.

4. The light detecting device according to claim 2 , wherein the signal charge generated by the first photoelectric conversion element comprises electrons.

5. The light detecting device according to claim 1 , wherein the first diffusion layer is configured to retain a signal charge generated by the first photoelectric conversion element.

6. The light detecting device according to claim 1 , wherein the first transistor is configured to output a signal charge in the first diffusion layer as a pixel signal when the pixel is selected by the second transistor.

7. The light detecting device according to claim 1 , wherein the second transistor is configured to control selecting of the pixel.

8. The light detecting device according to claim 1 , wherein the third transistor is configured to control a voltage of an output end of the first transistor.

9. The light detecting device according to claim 1 , wherein:

the first photoelectric conversion element photoelectrically converts light of a first wavelength; and

the pixel further comprises:

a second photoelectric conversion element which photoelectrically converts light of a second wavelength different from the first wavelength;

a second diffusion layer electrically coupled to the second photoelectric conversion element;

a fourth transistor, a gate of the fourth transistor being electrically coupled to the second diffusion layer; and

a fifth transistor, one of a source or a drain of the fifth transistor being electrically coupled to one of a source or a drain of the fourth transistor.

10. The light detecting device according to claim 9 , wherein the pixel further comprises a third photoelectric conversion element which is electrically coupled to the second diffusion layer and photoelectrically converts light of a third wavelength different from the first wavelength and the second wavelength.

11. The light detecting device according to claim 9 , wherein the pixel further comprises a sixth transistor, one of a source or a drain of the sixth transistor being electrically coupled to the one of the source or the drain of the fourth transistor and being electrically coupled to the one of the source or the drain of the fifth transistor.

12. The light detecting device according to claim 1 , wherein the first photoelectric conversion element is formed with a structure having a photoelectric conversion film interposed between upper and lower electrodes.

13. The light detecting device according to claim 1 , wherein the first photoelectric conversion element is formed with a photodiode formed by a PN junction in a semiconductor substrate.

14. The light detecting device according to claim 1 , wherein:

the first diffusion layer is of a second conductivity type, the first diffusion layer being formed in a semiconductor substrate of a first conductivity type; and

a reset voltage for resetting a voltage of the first diffusion layer is equal to a potential of the first conductivity type.

15. The light detecting device according to claim 14 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.

16. The light detecting device according to claim 1 , wherein the pixel further comprises a fourth transistor, one of a source or a drain of the fourth transistor being electrically coupled to the first photoelectric conversion element and the other of the source or the drain of the fourth transistor being electrically coupled to the first diffusion layer.

17. The light detecting device according to claim 1 , wherein the first diffusion layer is a floating diffusion.

18. The light detecting device according to claim 1 , wherein the third transistor is a deep-depletion transistor.

19. The light detecting device according to claim 1 , further comprising a driving circuit that applies a negative bias as an off-state voltage of the third transistor.

20. The light detecting device according to claim 1 , further comprising a driving circuit that controls the third transistor to be invariably in an off-state while the second transistor is in an on-state.

21. The light detecting device according to claim 1 , further comprising a driving circuit that switches off the third transistor before switching the second transistor on.

22. The light detecting device according to claim 1 , further comprising a driving circuit, wherein, after the driving circuit performs an operation to reset the first diffusion layer while the second transistor is in an on-state and the third transistor is in an off-state, the driving circuit performs an operation for signal accumulation by the first photoelectric conversion element while the second transistor is in an off-state and the third transistor is in an on-state.

23. The light detecting device according to claim 1 , further comprising a driving circuit, wherein, after the driving circuit performs an operation to reset the first diffusion layer while the second transistor is in an off-state and the third transistor is in an on-state, the driving circuit performs an operation to read out a signal at the time of the reset while the second transistor is in an on-state and the third transistor is in an off-state.

24. A method of driving a light detecting device comprising a pixel, the pixel comprising a first photoelectric conversion element, a first diffusion layer, a first transistor, a second transistor, and a third transistor, the method comprising:

the first photoelectric conversion element generating and accumulating signal charge by receiving light having entered the pixel and photoelectrically converting the light;

the first diffusion layer retaining the signal charge generated by the first photoelectric conversion element;

the first transistor outputting the signal charge in the first diffusion layer as a pixel signal when the pixel is selected by the second transistor;

the second transistor controlling selecting of the pixel; and

the third transistor controlling a voltage of an output end of the first transistor while the first photoelectric conversion element generates and accumulates the signal charge.

25. An electronic apparatus comprising a light detecting device comprising a pixel, the pixel comprising:

a first photoelectric conversion element;

a first diffusion layer electrically coupled to the first photoelectric conversion element;

a first transistor, a gate of the first transistor being electrically coupled to the first diffusion layer;

a second transistor, one of a source or a drain of the second transistor being electrically coupled to one of a source or a drain of the first transistor; and

a third transistor, one of a source or a drain of the third transistor being electrically coupled to the one of the source or the drain of the first transistor and being electrically coupled to the one of the source or the drain of the second transistor,

wherein the first transistor and the third transistor have a same channel type, and

wherein the other of the source or the drain of the first transistor and the other of the source or the drain of the third transistor are electrically coupled to a node that receives a power supply voltage so that, when the node is coupled to the power supply voltage, a voltage of the other of the source or the drain of the first transistor is equal to a voltage of the other of the source or the drain of the third transistor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2022
From: SONY CORPORATION
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 060423/0219 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2022
From: KOGA, FUMIHIKO
To: SONY CORPORATION
Reel/Frame 060150/0170 →
Priority Claims (1)
JP JP2014-051895 · Mar 14, 2014 · national
Continuity (5)
Continuation 16575829 · Sep 19, 2019
Continuation 16265403 · Feb 1, 2019
Continuation 15943077 · Apr 2, 2018
Continuation 15124204
Related Publication 20210203866A1 · Jul 1, 2021
Cited By (2)
US 12,495,629 US 12,588,303