IP Library Granted Patent US 11,576,261
Granted Patent B2
US 11,576,261 · App. 17/196,651 · Granted Feb 7, 2023

Connection structure embedded substrate

Inventors: Joo Hwan Jung (Suwon-si, KR); Jae Woong Choi (Suwon-si, KR); Seung Eun Lee (Suwon-si, KR); Yong Hoon Kim (Suwon-si, KR); Jin Won Lee (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H05K1/113H05K1/0313H05K1/115H05K1/142H05K1/181H05K1/0243H05K2201/09518
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Quick Facts
Patent No.
US 11,576,261
App. No.
17/196,651
Granted
Feb 7, 2023
Kind
B2
Abstract

A connection structure embedded substrate includes a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body; and a connection structure embedded in the first insulating body and including first and second substrates. The first and second substrates are disposed adjacent to each other.

Claims (65)

1. A connection structure embedded substrate, comprising:

a printed circuit board including a first insulating body and a plurality of first wiring layers disposed on at least one of an external region or an internal region of the first insulating body;

a connection structure embedded in the first insulating body and including first and second substrates; and

a connection via disposed between the first and second substrates and penetrating the connection structure,

wherein the first and second substrates are disposed adjacent to each other, and

wherein the connection via is spaced apart from each corner region of both the first and second substrates.

2. The connection structure embedded substrate of claim 1 , wherein the first and second substrates are disposed on the same level.

3. The connection structure embedded substrate of claim 2 ,

wherein each of the first and second substrates includes a second insulating body, and a plurality of second wiring layers disposed on at least one of an external region or an internal region of the second insulating body, and

wherein at least a portion of the plurality of second wiring layer is connected to the connection via.

4. The connection structure embedded substrate of claim 3 , wherein, a pitch of at least one of the plurality of first wiring layers is defined as a first pitch, a pitch of at least one of the plurality of second wiring layers is defined as a second pitch, and the first pitch is greater than the second pitch.

5. The connection structure embedded substrate of claim 3 , wherein, an average spacing between the plurality of first wiring layers is defined as a first spacing, an average spacing between the plurality of second wiring layers is defined as a second spacing, and the first spacing is greater than the second spacing.

6. The connection structure embedded substrate of claim 3 ,

wherein the first insulating body includes a plurality of first insulating layers, and

wherein the connection via further penetrates one of the plurality of first insulating layers and is connected to at least a portion of the plurality of first wiring layers.

7. The connection structure embedded substrate of claim 6 ,

wherein the second insulating body includes a plurality of second insulating layers, and

wherein a lower surface of a lowermost second insulating layer of the plurality of second insulating layers is in contact with one of the plurality of first insulating layers.

8. The connection structure embedded substrate of claim 7 , wherein the lowermost second insulating layer of the plurality of second insulating layers includes an Ajinomoto build-up film (ABF).

9. The connection structure embedded substrate of claim 7 , wherein an uppermost second wiring layer of the plurality of second wiring layers is buried in an upper side of an uppermost second insulating layer of the plurality of second insulating layers and an upper surface of the uppermost second wiring layer is exposed.

10. The connection structure embedded substrate of claim 9 , wherein the exposed upper surface of the uppermost second wiring layer of the plurality of second wiring layers is connected to at least a portion of one of the plurality of first wiring layers through a wiring via.

11. The connection structure embedded substrate of claim 6 , wherein at least a portion of the plurality of first wiring layers are disposed on one surface and the other surface of one of the plurality of first insulating layers, respectively.

12. The connection structure embedded substrate of claim 6 ,

wherein the printed circuit board further includes a plurality of first via layers penetrating at least a portion of the first insulating body and connecting the plurality of first wiring layers to each other,

wherein each of the first and second substrates includes a plurality of second via layers penetrating at least a portion of the second insulating body and connecting the plurality of second wiring layers to each other, and

wherein the connection via has a tapered shape tapered in a direction opposite to the plurality of second via layers.

13. The connection structure embedded substrate of claim 6 , further comprising:

a plurality of electronic components disposed on the printed circuit board,

wherein the connection structure is disposed on a level the same as a level of an uppermost first insulating layer of the plurality of first insulating layers, and

wherein at least a portion of each of the plurality of electronic components are connected to each other through the connection structure.

14. A connection structure embedded substrate, comprising:

a printed circuit board including a first insulating layer having a cavity, and a first wiring layer disposed on one surface and the other surface of the first insulating layer;

a connection structure including first and second substrates disposed in an internal portion of the cavity; and

a connection via penetrating at least a portion of each of the first and second substrates,

wherein the first and second substrates are disposed adjacent to each other, and

wherein the connection via is spaced apart from each corner region of both the first and second substrates.

15. The connection structure embedded substrate of claim 14 ,

wherein each of the first and second substrates includes a plurality of wiring layers, and

wherein the connection via is connected to the plurality of wiring layers.

16. The connection structure embedded substrate of claim 15 ,

wherein the printed circuit board further includes second and third insulating layers covering the one surface and the other surface of the first insulating layer, respectively, and second and third wiring layers disposed on the second and third insulating layers, and

wherein the connection via further penetrates at least one of the second and third insulating layers, and is connected to the second and third wiring layers.

17. A substrate, comprising:

a printed circuit board;

first and second substrates embedded in the printed circuit board; and

a connection via disposed between the first and second substrates and connecting the first and second substrates to each other,

wherein the connection via is spaced apart from each corner region of both the first and second substrates.

18. The substrate of claim 17 , wherein the connection via penetrates at least a portion of the first substrate and at least a portion of the second substrate.

19. The substrate of claim 17 , wherein the connection via connects the first substrate and the second substrate to one wiring layer of the printed circuit board.

20. The substrate of claim 19 , wherein the one wiring layer of the printed circuit board is disposed on the first substrate and the second substrate, and

the connection via connects the first substrate and the second substrate to another wiring layer of the printed circuit board below the first substrate and the second substrate.

21. The substrate of claim 17 , wherein the printed circuit board includes an insulating layer having a portion covering upper surfaces of the first substrate and the second substrate, and another portion disposed between the first substrate and the second substrate.

22. The substrate of claim 21 , wherein the connection via penetrates through the portion of the insulating layer disposed between the first substrate and the second substrate.

23. The substrate of claim 21 , further comprising wiring vias extending in the portion of the insulating layer covering the first substrate and the second substrate, and connected to wiring layers of the first substrate and the second substrate, respectively.

24. The substrate of claim 23 , wherein a tapered direction of vias in one of the first substrate and the second substrate is opposite to a tapered direction of the wiring vias and a tapered direction of the connection via.

25. A connection structure embedded substrate, comprising:

a printed circuit board including a plurality of first wiring layers;

a connection structure embedded in the printed circuit board and including a plurality of second wiring layers; and

a connection via extending between two of the plurality of first wiring layers to penetrate through the connection structure, thereby connecting one or more of the plurality of second wirings layers to the two of the plurality of first wiring layers.

26. The connection structure embedded substrate of claim 25 , wherein the connection structure is disposed between the two of the plurality of first wiring layers.

27. The connection structure embedded substrate of claim 25 , wherein a pitch of at least one of the plurality of first wiring layers is greater than a pitch of at least one of the plurality of second wiring layers.

28. The connection structure embedded substrate of claim 25 , wherein the connection structure includes an Ajinomoto build-up film (ABF) in contact with the printed circuit board.

29. The connection structure embedded substrate of claim 25 , wherein an uppermost second wiring layer of the plurality of second wiring layers is buried in an uppermost insulating layer of the connection structure, and an upper surface of the uppermost second wiring layer is exposed from the uppermost insulating layer of the connection structure.

30. The connection structure embedded substrate of claim 29 , further comprising a wiring via connecting one of the two of the plurality of first wiring layers to the uppermost second wiring layer.

31. The connection structure embedded substrate of claim 30 , wherein a tapered direction of vias in the connection structure is opposite to a tapered direction of the wiring via and a tapered direction of the connection via.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE TO ADD THE FIFTH INVENTOR JIN WON LEE PREVIOUSLY RECORDED ON REEL 055540 FRAME 0113. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 11, 2021
From: JUNG, JOO HWAN; CHOI, JAE WOONG; LEE, SEUNG EUN; KIM, YONG HOON; LEE, JIN WON
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 055558/0927 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2021
From: JUNG, JOO HWAN; CHOI, JAE WOONG; LEE, SEUNG EUN; KIM, YONG HOON
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 055540/0113 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2021
From: JUNG, JOO HWAN; CHOI, JAE WOONG; LEE, SEUNG EUN; KIM, YONG HOON; LEE, JIN WON
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 055540/0484 →
Priority Claims (1)
KR 10-2020-0176666 · Dec 16, 2020 · national
Continuity (1)
Related Publication 20220192020A1 · Jun 16, 2022
Cited By (1)
US 12,309,934