Display with hybrid oxide gate driver circuitry having multiple low power supplies
A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
1. A display comprising:
an array of pixels; and
a chain of gate driver circuits configured to provide gate output signals to the array of pixels, wherein each gate driver circuit in the chain of gate driver circuits comprises:
an output buffer sub-circuit powered by a first positive power supply voltage and a first ground power supply voltage; and
a logic sub-circuit powered by a second positive power supply voltage and a second ground power supply voltage, wherein the first positive power supply voltage is less than the second positive power supply voltage and wherein the first ground power supply voltage is greater than the second ground power supply voltage.
2. The display of claim 1 , wherein the output buffer sub-circuit is configured to generate one of the gate output signals and wherein the logic sub-circuit is configured to generate a carry output signal that is fed to another gate driver circuit in the chain.
3. The display of claim 1 , wherein all transistors in the chain of gate driver circuits comprise semiconducting oxide transistors having channels formed from semiconducting oxide material.
4. The display of claim 1 , wherein the output buffer sub-circuit comprises first and second semiconducting oxide transistors that are coupled in series between the first positive power supply voltage and the first ground power supply voltage and that exhibit a first mobility.
5. The display of claim 4 , wherein the logic sub-circuit comprises a first subset of semiconducting oxide transistors that exhibit the first mobility and a second subset of semiconducting oxide transistors that exhibit a second mobility that is less than the first mobility.
6. The display of claim 4 , wherein the logic sub-circuit comprises:
a carry circuit configured to generate a carry output signal;
a voltage setting circuit coupled to a gate terminal of the first semiconducting oxide transistor;
an inverter circuit coupled to a gate terminal of the second semiconducting oxide transistor; and
a discharging circuit configured to discharge at least the gate terminal of the first semiconducting oxide transistor.
7. The display of claim 6 , wherein the carry circuit comprises a semiconducting oxide transistor having a drain terminal coupled to the second positive power voltage, a gate terminal coupled to the gate terminal of the first semiconducting oxide transistor, and a source terminal on which the carry output signal is generated.
8. The display of claim 6 , wherein the carry circuit comprises a semiconducting oxide transistor having a drain terminal configured to receive one of the gate output signals from a preceding gate driver circuit in the chain, a gate terminal coupled to the gate terminal of the first semiconducting oxide transistor, and a source terminal on which the carry output signal is generated.
9. The display of claim 6 , wherein the inverter circuit comprises:
a third semiconducting oxide transistor coupled to the second positive power supply terminal;
a fourth semiconducting oxide transistor configured to receive a carry output signal from a preceding gate driver circuit in the chain; and
a fifth semiconducting oxide transistor coupled in parallel with the fourth semiconducting-oxide transistor.
10. The display of claim 6 , wherein the inverter circuit comprises:
a third semiconducting oxide transistor configured to receive a clock signal;
a fourth semiconducting oxide transistor configured to receive a carry output signal from a preceding gate driver circuit in the chain; and
a fifth semiconducting oxide transistor coupled in series with the third semiconducting oxide transistor.
11. The display of claim 6 , wherein the inverter circuit comprises:
a third semiconducting oxide transistor having a drain terminal coupled to the second positive power supply terminal and having a gate terminal configured to receive a reference voltage;
a fourth semiconducting oxide transistor configured to receive a carry output signal from a preceding gate driver circuit in the chain; and
a fifth semiconducting oxide transistor coupled in parallel with the fourth semiconducting-oxide transistor.
12. The display of claim 6 , wherein the discharging circuit comprises a semiconducting oxide transistor having a drain terminal coupled to the gate terminal of the first semiconducting oxide transistor, a source terminal coupled to the second ground power supply voltage, and a gate terminal configured to receive a clear signal.
13. The display of claim 6 , wherein the discharging circuit comprises:
a third semiconducting oxide transistor having a drain terminal coupled to the gate terminal of the first semiconducting oxide transistor, a source terminal coupled to the second ground power supply voltage, and a gate terminal configured to receive a clear signal;
a fourth semiconducting oxide transistor having a drain terminal coupled to the gate terminal of the second semiconducting oxide transistor, a source terminal coupled to the second ground power supply voltage, and a gate terminal configured to receive the clear signal; and
a fifth semiconducting oxide transistor having a drain terminal coupled to a source terminal of the first semiconducting oxide transistor, a source terminal coupled to the first ground power supply voltage, and a gate terminal configured to receive the clear signal.
14. A display comprising:
an array of pixels; and
a plurality of gate driver circuits configured to control the array of pixels, wherein at least one gate driver circuit in the plurality of gate driver circuits comprises:
an output buffer sub-circuit configured to generate a gate output signal and having a first group of semiconducting oxide transistors exhibiting a first mobility; and
a logic sub-circuit configured to generate a carry output signal and having a second group of semiconducting oxide transistors exhibiting a second mobility that is less than the first mobility.
15. The display of claim 14 , wherein:
the output buffer sub-circuit is powered by a first positive power supply voltage and a first ground power supply voltage; and
the logic sub-circuit is powered by a second positive power supply voltage different than the first positive power supply voltage and by a second ground power supply voltage different than the first ground power supply voltage.
16. The display of claim 15 , wherein the first positive power supply voltage is less than the second positive power supply voltage and wherein the first ground power supply voltage is greater than the second ground power supply voltage.
17. The display of claim 14 , wherein the logic sub-circuit further includes a third group of semiconducting oxide transistors exhibiting the first mobility.
18. A display gate driver circuit comprising:
a first semiconducting oxide transistor having a drain terminal coupled to a first positive power supply voltage, a source terminal on which a gate output signal is generated, and a gate terminal;
a second semiconducting oxide transistor having a drain terminal coupled to the source terminal of the first semiconducting oxide transistor, a source terminal coupled to a first ground power supply voltage, and a gate terminal; and
a third semiconducting oxide transistor having a drain terminal configured to receive a carry output signal from another display gate driver circuit, a gate terminal configured to receive a clock signal, and a source terminal coupled to the gate terminal of the first semiconducting oxide transistor, wherein the first and second semiconducting oxide transistors have a first mobility and wherein the third semiconducting oxide transistor has a second mobility less than the first mobility.
19. The display gate driver circuit of claim 18 , further comprising:
a fourth semiconducting oxide transistor having a gate terminal coupled to the gate terminal of the first semiconducting oxide transistor and having a source terminal on which an additional carry output signal is generated.
20. The display gate driver circuit of claim 19 , further comprising:
an inverter having an output coupled to the gate terminal of the second semiconducting oxide transistor.
21. The display gate driver circuit of claim 20 , further comprising:
a discharge circuit configured to discharge at least one of the gate terminal of the first semiconducting oxide transistor and the gate terminal of the second semiconducting oxide transistor.