IP Library Granted Patent US 11,581,237
Granted Patent B2
US 11,581,237 · App. 16/012,126 · Granted Feb 14, 2023

Cooling apparatuses for microelectronic assemblies

Inventors: Joe F. Walczyk (Tigard, OR); Pooya Tadayon (Portland, OR)
Assignee: Intel Corporation
H01L23/3675H01L21/4882H01L23/3677H01L23/46H01L23/3736
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Quick Facts
Patent No.
US 11,581,237
App. No.
16/012,126
Granted
Feb 14, 2023
Kind
B2
Abstract

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate; and a cooling apparatus that may include a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die, and a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns.

Claims (28)

1. A microelectronic assembly, comprising:

a package substrate having a surface;

a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the surface of the package substrate;

a cooling apparatus, comprising:

a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in thermal contact with the second surface of the die;

a plurality of conductive structures on the second surface of the conductive base, wherein an individual conductive structure of the plurality of conductive structures has a width between 10 microns and 100 microns; and

at least two conductive features extending from the first surface of the conductive base attached to the surface of the package substrate; and

a conductive lid, wherein the conductive lid is on a top surface of the plurality of conductive structures, and wherein the conductive lid forms a cavity around the plurality of conductive structures.

2. The microelectronic assembly of claim 1 , wherein individual conductive structures of the plurality of conductive structures have a height between 1 mm and 2 mm.

3. The microelectronic assembly of claim 1 , wherein an individual one of the plurality of conductive structures has an aspect ratio between 10:1 and 20:1.

4. The microelectronic assembly of claim 1 , wherein a channel between adjacent individual ones of the conductive structures has a width between 10 microns and 200 microns.

5. The microelectronic assembly of claim 1 , wherein at least one of the plurality of conductive structures is a vertical fin.

6. The microelectronic assembly of claim 5 , wherein the vertical fin has a surface that is non-linear.

7. The microelectronic assembly of claim 1 , wherein at least one of the plurality of conductive structures is a pillar.

8. The microelectronic assembly of claim 1 , wherein a first individual one of the plurality of conductive structures is a pillar and a second individual one of the plurality of conductive structures is a vertical fin.

9. The microelectronic assembly of claim 1 , further comprising:

a fluid in the cavity.

10. A microelectronic assembly, comprising:

a package substrate having a first surface and an opposing second surface;

a die having a first surface and an opposing second surface, wherein the first surface of the die is coupled to the second surface of the package substrate;

a cooling apparatus, comprising:

a conductive base having a first surface and an opposing second surface, wherein the first surface of the conductive base is in contact with the second surface of the die;

a plurality of conductive structures on the second surface of the conductive base, wherein the plurality of conductive structures are attached to the second surface of the conductive base; and

at least two conductive features extending from the first surface of the conductive base attached to the second surface of the package substrate; and

a conductive seed layer between the second surface of the conductive base and the plurality of conductive structures.

11. The microelectronic assembly of claim 10 , wherein the conductive base includes a first material and the plurality of conductive structures include a second material different from the first material.

12. The microelectronic assembly of claim 11 , wherein the first material includes copper.

13. The microelectronic assembly of claim 11 , wherein the second material includes nickel.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2018
From: WALCZYK, JOE F; TADAYON, POOYA
To: INTEL CORPORATION
Reel/Frame 046130/0560 →
Continuity (1)
Related Publication 20190385925A1 · Dec 19, 2019