Semiconductor devices including semiconductor pattern

1. A semiconductor device comprising:

a first conductive line extending in a horizontal direction;

a second conductive line spaced apart from the first conductive line in the horizontal direction and extending in a vertical direction;

a semiconductor pattern disposed between the first conductive line and the second conductive line, the semiconductor pattern including:

a first semiconductor pattern disposed adjacent to the first conductive line, the first semiconductor pattern having first-conductivity-type impurities;

a second semiconductor pattern disposed adjacent to the second conductive line, the second semiconductor pattern having second-conductivity-type impurities that are different from the first-conductivity-type impurities; and

a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern, the third semiconductor pattern including a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region comprises an intrinsic semiconductor layer, wherein the first to third semiconductor patterns are contiguously arranged in the horizontal direction;

a first gate line crossing the first region and extending in the vertical direction; and

a second gate line crossing the second region and extending in the vertical direction.

2. The semiconductor device according to claim 1 , wherein each of the first region and the second region comprises the intrinsic semiconductor layer.

3. The semiconductor device according to claim 1 , wherein:

the first region comprises the intrinsic semiconductor layer; and

the second region comprises a semiconductor layer having the first-conductivity-type impurities.

4. The semiconductor device according to claim 1 , wherein:

the first region comprises a semiconductor layer having the second-conductivity-type impurities; and

the second region comprises the intrinsic semiconductor layer.

5. The semiconductor device according to claim 1 , wherein the second region is in continuity with the first region.

6. The semiconductor device according to claim 1 , wherein each of the first semiconductor pattern, the second semiconductor pattern and the third semiconductor pattern comprises at least one compound selected from silicon, germanium, silicon-germanium, and indium gallium zinc oxide (IGZO).

7. The semiconductor device according to claim 1 , wherein the third semiconductor pattern further comprises a third region, the third region is disposed between the first region and the first semiconductor pattern or between the second region and the second semiconductor pattern.

8. The semiconductor device according to claim 7 , further comprising:

a selection gate line crossing the third region.

9. The semiconductor device according to claim 7 , wherein the third region comprises the intrinsic semiconductor layer.

10. The semiconductor device according to claim 7 , wherein the third region comprises a semiconductor layer having the first-conductivity-type impurities.

11. A semiconductor device comprising:

a plurality of semiconductor patterns disposed on a substrate, each of the plurality of semiconductor patterns extending in a first direction that is parallel to an upper surface of the substrate, each of the plurality of semiconductor patterns including:

a first semiconductor pattern having first-conductivity-type impurities, a second semiconductor pattern having second-conductivity-type impurities that are different from the first-conductivity-type impurities, and a third semiconductor pattern disposed between the first semiconductor pattern and the second semiconductor pattern, wherein the first to third semiconductor patterns are contiguously arranged in the first direction,

the third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern, wherein at least one of the first region and the second region comprises an intrinsic semiconductor layer;

a first conductive line connected to the plurality of semiconductor patterns and extending in a second direction that is perpendicular to the upper surface of the substrate;

a plurality of second conductive lines spaced apart from the first conductive line in the first direction, each of the plurality of second conductive lines extending in a third direction that is parallel to the upper surface of the substrate and crosses the first direction, each of the second conductive lines is connected to a corresponding one of the plurality of semiconductor patterns;

a first gate line disposed adjacent to the plurality of semiconductor patterns and extending in the second direction; and

a second gate line disposed adjacent to the plurality of semiconductor patterns, the second gate line extending in the second direction and is parallel to the first gate line,

wherein the first gate line crosses the first region, and the second gate line crosses the second region.

12. The semiconductor device according to claim 11 , Wherein each of the first region and the second region comprises the intrinsic semiconductor layer.

13. The semiconductor device according to claim 11 , wherein the third semiconductor pattern further comprises a third region, the third region is disposed between the first region and the first semiconductor pattern or between the second region and the second semiconductor pattern.

14. The semiconductor device according to claim 13 , further comprising:

a selection gate line disposed adjacent to the plurality of semiconductor patterns, the selection gate line extending in the second direction and is parallel to the first gate line and the second gate line,

wherein the selection gate line crosses the third region.

15. The semiconductor device according to claim 13 , wherein the third region comprises the intrinsic semiconductor layer.