Display panel including a signal line having a two-layer structure, and method for manufacturing the same

1. A display panel comprising:

a base layer;

a signal line on the base layer and comprising

a first layer comprising aluminum, and

a second layer directly on the first layer and consisting of niobium;

a first thin film transistor connected to the signal line;

a second thin film transistor on the base layer;

a capacitor electrically connected to the second thin film transistor; and

a light emitting element electrically connected to the second thin film transistor.

2. The display panel of claim 1 , wherein the first thin film transistor comprises:

a first polysilicon semiconductor on the base layer;

a first control electrode overlapping the first polysilicon semiconductor and connected to the signal line; and

a first input electrode and a first output electrode, each connected to the first polysilicon semiconductor.

3. The display panel of claim 2 , wherein the first control electrode has the same stacked structure as the signal line.

4. The display panel of claim 2 , wherein the second thin film transistor comprises:

a second polysilicon semiconductor on the base layer;

a second control electrode overlapping the second polysilicon semiconductor and on a different layer than the first control electrode; and

a second input electrode and a second output electrode, each connected to the second polysilicon semiconductor.

5. The display panel of claim 4 , wherein the capacitor comprises a first electrode on the same layer as the signal line and a second electrode on the same layer as the second control electrode, and

wherein the first electrode has the same stacked structure as the signal line.

6. The display panel of claim 5 , wherein each of the second control electrode and the second electrode comprises

a first layer comprising aluminum, and

a second layer directly on the first layer and consisting of niobium.

7. The display panel of claim 1 , wherein the first layer comprises an aluminum (Al)-nickel (Ni)-lanthanum (La) alloy.

8. The display panel of claim 7 , wherein a content of the nickel in the first layer is 0.01 at % to 0.05 at %, and a content of the lanthanum in the first layer is 0.02 at % to 0.05 at %.

9. The display panel of claim 1 , wherein a line width of the signal line is 3 μm to 5 μm.

10. The display panel of claim 1 , wherein a thickness of the first layer is 1000 Å to 2000 Å, and a thickness of the second layer is 200 Å to 600 Å.

11. The display panel of claim 1 , wherein stress generated in the signal line is −250 Mpa to −480 Mpa.

12. The display panel of claim 1 , wherein the signal line is configured to provide a turn-on signal to the first thin film transistor.

13. A display panel comprising:

a base layer;

a first thin film transistor on the base layer;

a second thin film transistor electrically connected to the first thin film transistor; and

a light emitting element connected to the second thin film transistor,

wherein the first thin film transistor comprises:

a first polysilicon semiconductor on the base layer;

a first control electrode overlapping the first polysilicon semiconductor and comprising a first layer comprising an aluminum (Al)-nickel (Ni)-lanthanum (La) alloy and a second layer directly on the first layer and consisting of niobium; and

a first input electrode and a first output electrode, each connected to the first polysilicon semiconductor.

14. A method for manufacturing a display panel, the method comprising:

forming a semiconductor pattern on a base layer;

forming a signal line on the base layer;

forming, on the base layer, a control electrode overlapping the semiconductor pattern;

forming, on the base layer, an input electrode and an output electrode which are connected to the semiconductor pattern; and

forming a light emitting element on the base layer,

wherein the forming of the signal line comprises:

forming a first layer comprising aluminum;

forming, directly on the first layer, a second layer consisting of niobium; and

patterning the first layer and the second layer.

15. The method of claim 14 , wherein the first layer comprises an aluminum (Al)-nickel (Ni)-lanthanum (La) alloy.

16. The method of claim 15 , wherein a content of the nickel in the first layer is 0.01 at % to 0.05 at %, and a content of the lanthanum in the first layer is 0.02 at % to 0.05 at %.

17. The method of claim 14 ,

wherein the semiconductor pattern comprises a polysilicon semiconductor, and

the method further comprises doping an area of the polysilicon semiconductor, which does not overlap the control electrode, with an impurity.

18. The method of claim 17 , further comprising annealing the polysilicon semiconductor at 400° C. or higher.

19. The method of claim 17 , further comprising:

forming, on the base layer, an insulating layer configured to cover the polysilicon semiconductor;

forming, in the insulating layer, a through-hole that exposes the area of the polysilicon semiconductor which does not overlap the control electrode; and

cleaning the area of the polysilicon semiconductor exposed by the through-hole.

20. The method of claim 14 , wherein the forming of the second layer is performed through plasma deposition, and

the plasma deposition is performed under deposition conditions with a chamber pressure of 0.16 Pa to 0.2 Pa and a power density of 2.68 W/cm 2 to 3.13 W/cm 2 .