Negative capacitance transistor with a diffusion blocking layer

1. A semiconductor device, comprising:

a substrate;

a first layer disposed over a portion of the substrate, wherein the first layer contains a dielectric material having a dielectric constant greater than a dielectric constant of silicon oxide;

a second layer disposed over the first layer, wherein the second layer contains a metal oxide or a metal nitride, wherein the second layer includes a plurality of sub-layers that each have a different material composition; and

a third layer disposed over the second layer, wherein the third layer contains a ferroelectric material;

wherein the first layer, the second layer, and the third layer are portions of a gate.

2. The semiconductor device of claim 1 , wherein the gate is a gate of a negative capacitance transistor.

3. The semiconductor device of claim 1 , further comprising a metal-containing gate electrode disposed over the third layer.

4. The semiconductor device of claim 1 , wherein the second layer contains: aluminum oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, aluminum nitride, tantalum nitride, titanium nitride, lanthanum nitride, or praseodymium nitride.

5. The semiconductor device of claim 1 , wherein the ferroelectric material includes an oxide material doped with a dopant.

6. The semiconductor device of claim 5 , wherein:

the oxide material of the ferroelectric material includes: hafnium zirconium oxide, hafnium silicon oxide, hafnium aluminum oxide, lead zirconium titanium oxide, or barium titanium oxide; and

the dopant of the ferroelectric material includes zirconium, silicon, aluminum, lead, barium, titanium, or a polymer.

7. The semiconductor device of claim 1 , wherein:

at least one of the sub-layers of the second layer contains aluminum oxide; and

the third layer contains a hafnium-based material doped with a zirconium dopant.

8. The semiconductor device of claim 1 , wherein the second layer has a dielectric constant in a range between about 15 and about 60.

9. The semiconductor device of claim 1 , wherein a thickness of the second layer is in a range between about 1 nanometer and about 3 nanometers.

10. A semiconductor device, comprising:

a substrate;

a high-k dielectric layer disposed over a portion of the substrate, wherein the high-k dielectric layer contains a dielectric material having a dielectric constant greater than a dielectric constant of silicon oxide;

a plurality of diffusion-blocking layers disposed over the high-k dielectric layer, wherein each of the diffusion-blocking layers contains a metal oxide or a metal nitride, and wherein the diffusion-blocking layers have different material compositions from one another; and

a ferroelectric layer disposed over the diffusion-blocking layers, wherein the ferroelectric layer has a different material composition than each of the diffusion-blocking layers; and

a metal gate electrode disposed over the ferroelectric layer.

11. The semiconductor device of claim 10 , wherein each of the diffusion-blocking layers contains: aluminum oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, aluminum nitride, tantalum nitride, titanium nitride, lanthanum nitride, or praseodymium nitride.

12. The semiconductor device of claim 10 , wherein the ferroelectric layer includes a hafnium-based material that is doped with zirconium, silicon, aluminum, lead, barium, titanium, or a polymer.

13. The semiconductor device of claim 10 , wherein the diffusion layers each have a dielectric constant in a range between about 15 and about 60.

14. The semiconductor device of claim 10 , the ferroelectric layer contains a hafnium-based material doped with a zirconium dopant.

15. A method, comprising:

depositing a dielectric layer over a channel region of a transistor, wherein the dielectric layer contains a dielectric material having a dielectric constant greater than a dielectric constant of silicon oxide;

depositing a diffusion-blocking structure that includes a plurality of diffusion-blocking layers over the dielectric layer, wherein the diffusion-blocking layers each contains a metal oxide or a metal nitride material, and wherein the diffusion-blocking layers each have a different material composition;

depositing a hafnium-based layer over the diffusion-blocking structure, and wherein the hafnium-based layer has a different material composition than the diffusion-blocking structure;

doping the hafnium-based layer with a dopant; and

performing a first annealing process during or after the depositing of the hafnium-based layer, wherein the first annealing process causes the dopant to diffuse out of the hafnium-based layer.

16. The method of claim 15 , wherein the diffusion-blocking structure reduces a diffusion of the dopant from the hafnium-based layer into the dielectric layer during the first annealing process.

17. The method of claim 15 , further comprising: forming a metal gate electrode over the hafnium-based layer, wherein the forming of the metal gate electrode includes performing a second annealing process.

18. The method of claim 17 , wherein the diffusion-blocking structure reduces a diffusion of the dopant from the hafnium-based layer into the dielectric layer during the second annealing process.

19. The method of claim 15 , wherein the depositing the diffusion-blocking structure comprises depositing aluminum oxide, tantalum oxide, titanium oxide, lanthanum oxide, praseodymium oxide, aluminum nitride, tantalum nitride, titanium nitride, lanthanum nitride, or praseodymium nitride as the diffusion-blocking structure.

20. The method of claim 15 , wherein the doping comprises doping the hafnium-based layer with zirconium, silicon, aluminum, lead, barium, titanium, or a polymer.