Analog-to-digital converter circuit

1. An analog-to-digital converter (ADC) circuit, comprising:

a global input configured to receive an input voltage;

a plurality of converter circuits, wherein each converter circuit ( 105 j ) comprises:

a comparator circuit having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit; and

a one-bit current-output digital-to-analog converter (DAC) having an input directly controlled from the output of the comparator circuit and an output connected to the second input of the comparator circuit;

wherein the second inputs of all comparator circuits are interconnected; and

wherein the ADC circuit comprises a digital output circuit configured to generate an output signal of the ADC circuit in response to the one-bit output signals of the comparator circuits.

2. The ADC circuit of claim 1 , wherein the ADC circuit comprises a capacitor circuit connected to the interconnected second inputs of the comparator circuits.

3. The ADC circuit of claim 1 , wherein the second inputs of the comparator circuits are formed by gate terminals of field-effect transistors.

4. The ADC circuit of claim 1 , wherein the comparator circuit is a clocked comparator circuit configured to update the output signal of the comparator circuit periodically in response to a clock signal.

5. The ADC circuit of claim 1 , wherein the digital output circuit comprises a digital summation circuit configured to generate a sum signal y[n] as a sum of the one-bit output signals from the comparator circuits.

6. The ADC circuit of claim 5 , wherein the digital output circuit comprises a filter circuit configured to generate a filtered sum signal by filtering the sum signal.

7. The ADC circuit of claim 6 , wherein the filter circuit is an accumulator.

8. The ADC circuit of claim 6 , wherein the filtered sum signal is the output signal of the ADC circuit.

9. The ADC circuit of claim 8 , wherein the digital output circuit comprises a mapping circuit configured to generate a mapped sum signal ê[n] in response to the sum signal y[n] as ê[n]=cdf −1 (y[n+1]), where cdf −1 (⋅) in an inverse of a monotone nonlinear mapping cdf(⋅).

10. The ADC circuit of claim 9 , wherein a sum of the mapped sum signal ê[n] and the filtered sum signal is the output signal of the ADC circuit.

11. An integrated circuit, comprising:

an analog-to-digital converter (ADC) circuit, the ADC circuit comprising:

a global input configured to receive an input voltage;

a plurality of converter circuits, wherein each converter circuit ( 105 j ) comprises:

a comparator circuit having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit; and

a one-bit current-output digital-to-analog converter (DAC) having an input directly controlled from the output of the comparator circuit and an output connected to the second input of the comparator circuit;

wherein the second inputs of all comparator circuits are interconnected; and

wherein the ADC circuit comprises a digital output circuit configured to generate an output signal of the ADC circuit in response to the one-bit output signals of the comparator circuits.

12. An electronic apparatus, comprising:

an analog-to-digital converter (ADC) circuit, the ADC circuit comprising:

a global input configured to receive an input voltage;

a plurality of converter circuits, wherein each converter circuit ( 105 j ) comprises:

a comparator circuit having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit; and

a one-bit current-output digital-to-analog converter (DAC) having an input directly controlled from the output of the comparator circuit and an output connected to the second input of the comparator circuit;

wherein the second inputs of all comparator circuits are interconnected; and

wherein the ADC circuit comprises a digital output circuit configured to generate an output signal of the ADC circuit in response to the one-bit output signals of the comparator circuits.

13. The electronic apparatus circuit of claim 12 , wherein the ADC circuit comprises a capacitor circuit connected to the interconnected second inputs of the comparator circuits.

14. The electronic apparatus circuit of claim 12 , wherein the second inputs of the comparator circuits are formed by gate terminals of field-effect transistors.

15. The electronic apparatus circuit of claim 12 , wherein the comparator circuit is a clocked comparator circuit configured to update the output signal of the comparator circuit periodically in response to a clock signal.

16. The electronic apparatus circuit of claim 12 , wherein the digital output circuit comprises a digital summation circuit configured to generate a sum signal y[n] as a sum of the one-bit output signals from the comparator circuits.

17. The electronic apparatus circuit of claim 12 :

wherein the digital output circuit comprises a filter circuit configured to generate a filtered sum signal by filtering the sum signal; and

wherein the filtered sum signal is the output signal of the ADC circuit.

18. The electronic apparatus of claim 12 , wherein the electronic apparatus is a communication apparatus.

19. The electronic apparatus of claim 18 , wherein the communication apparatus is a wireless communication device for a cellular communications system.

20. The electronic apparatus of claim 18 , wherein the communication apparatus is a base station for a cellular communications system.