Power control based on performance modification through pulse modulation
Systems and methods for power control based on performance modification through pulse modulation include an integrated circuit (IC) that may evaluate certain limit conditions within a computing device and compare the limit conditions to corresponding predefined thresholds. When a given predefined threshold is exceeded, an overage signal may be sent to a limits management circuit within the initial IC or another IC. The limits management circuit may generate a single-bit throttle signal through a pulse modulation circuit. The single-bit throttle signal may modify internal processing of an associated processor, which in turn changes power consumption.
1. An integrated circuit (IC) configured to be placed in a computing device, the IC comprising:
a limits management circuit comprising:
a pulse modulator circuit configured to convert a multi-bit overage signal to a single-bit throttle signal;
a random number generator (RNG) circuit coupled to the pulse modulator circuit; and
an output port configured to output the single-bit throttle signal; and
a processing circuit coupled to the output port and comprising a scheduler circuit configured to modify behavior of the processing circuit responsive to the single-bit throttle signal, wherein the scheduler circuit is configured to change performance based on the single-bit throttle signal.
2. The IC of claim 1 , wherein the scheduler circuit is configured to stall or unstall a pipeline responsive to the single-bit throttle signal.
3. The IC of claim 1 , wherein the scheduler circuit is configured to clock gate or clock ungate a pipeline responsive to the single-bit throttle signal.
4. The IC of claim 1 , wherein the scheduler circuit is configured to reduce performance.
5. The IC of claim 1 , wherein the scheduler circuit is configured to increase performance.
6. The IC of claim 1 , wherein the RNG circuit is configured to provide a random value used by a summation circuit in the pulse modulator circuit.
7. The IC of claim 1 , further comprising an over-limits table configured to generate the multi-bit overage signal.
8. A computing device comprising:
a first integrated circuit (IC), the first IC comprising:
a limits management circuit comprising:
a pulse modulator circuit configured to convert a multi-bit overage signal to a single-bit throttle signal; and
an output port configured to output the single-bit throttle signal; and
a processing circuit coupled to the output port and comprising a scheduler circuit configured to modify behavior of the processing circuit responsive to the single-bit throttle signal, wherein the scheduler circuit is configured to change performance of the processing circuit;
a second IC comprising:
memory configured to contain an over-limits table configured to contain configurable thresholds used to generate the multi-bit overage signal; and
a summation circuit configured to receive information indicative of per-device current consumption and sum the information, the summation circuit further configured to store the summed information in the over-limits table; and
one or more current sensors configured to provide a respective per-device current consumption signal to the summation circuit.
9. The computing device of claim 8 , further comprising a temperature sensor configured to provide a temperature signal to the over-limits table.
10. The computing device of claim 8 , wherein the one or more current sensors comprise one or more analog current sensors.
11. The computing device of claim 8 , wherein the one or more current sensors comprise one or more digital power meters.
12. The computing device of claim 8 , wherein the multi-bit overage signal is based on target performance and power and information indicating how much a measured value of a limit condition exceeds one of the configurable thresholds.
13. An integrated circuit (IC) configured to be placed in a computing device, the IC comprising:
a limits management circuit comprising:
an input port configured to receive a multi-bit overage signal;
a modulator coupled to the input port and configured to create a pulse modulated (PM) single-bit throttle signal;
a random number generator (RNG) circuit coupled to the modulator, and
an output port configured to output the PM single-bit throttle signal; and
a processing circuit configured to receive the PM single-bit throttle signal and stall operation based on the PM single-bit throttle signal.
14. The IC of claim 13 , further comprising a local current sensor configured to provide a local current level to an over-limits table.
15. The IC of claim 13 , wherein the RNG circuit is configured to generate a reference value used by the modulator.
16. The IC of claim 13 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.
17. A method for modifying performance of an integrated circuit (IC), the method comprising:
receiving a multi-bit overage signal indicative of over-limit levels within a computing device;
pulse modulating the multi-bit overage signal to a single-bit throttle signal by using a random value in the pulse modulating; and
controlling a processing circuit in the IC to change performance of the processing circuit with the single-bit throttle signal.
18. The method of claim 17 , wherein controlling the processing circuit comprises injecting a no-operation (NOP) code.
19. The method of claim 17 , wherein using the random value in the pulse modulating modulation comprises injecting the random value when determining when to sample a compare value.
20. The method of claim 17 , further comprising changing power consumption by varying the performance of the processing circuit.
21. The method of claim 17 , further comprising creating fairness across threads in a multi-threaded processor in the computing device through randomized pulse modulation of the multi-bit overage signal.
22. The method of claim 21 , further comprising creating fairness in accessing any shared resource in the computing device through randomized pulse modulation of the multi-bit overage signal.
23. The method of claim 17 , further comprising creating fairness across processors in a multi-processor system in the computing device through randomized pulse modulation of the multi-bit overage signal.
24. The method of claim 17 , wherein pulse modulating comprises using a delta-sigma modulator to pulse modulate.
25. The method of claim 24 , wherein using the delta-sigma modulator comprises using a random number generator (RNG) circuit to inject a random number.
26. The method of claim 17 , wherein pulse modulating comprises:
generating a difference between an input multi-bit signal with a generated impulse value;
generating the impulse value based on a selector; and
accumulating the difference using an integrator.
27. The method of claim 26 , further comprising injecting the random value into the pulse modulating.
28. The method of claim 27 , wherein injecting the random value comprises injecting the random value at an accumulator or at a sampling point.
29. The method of claim 17 , wherein pulse modulating comprises using a comparison circuit to compare an input to a reference value.
30. The method of claim 29 , further comprising generating the reference value using one of: a circuit producing a finite constant or a random number generator (RNG) circuit.