Command-triggered data clock distribution
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
1. A method of controlling an integrated-circuit memory component (“memory IC”), the method comprising:
outputting, to a first clock input of the memory IC, a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
outputting, to a second clock input of the memory IC, a data clock signal that toggles at a second frequency at least twice the first frequency; and
during an initial portion of the first interval while distribution of the data clock signal within a data interface of the memory IC is disabled, outputting a memory access command to the memory IC, synchronously with respect to the command/address clock signal, to enable distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval.
2. The method of claim 1 wherein outputting the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises outputting the memory access command to enable execution, within the data interface of the memory IC, of either a write data reception operation specified by the memory access command or a read data transmission operation specified by the memory access command.
3. The method of claim 1 wherein outputting the memory access command to enable distribution of the data clock signal within the data interface of the memory IC comprises outputting the memory access command to enable conduction of the data clock signal to timing inputs of at least one of data reception circuitry or data transmission circuitry within the data interface of the memory IC.
4. The method of claim 1 wherein outputting the memory access command to enable distribution of the data clock signal within the data interface of the memory IC comprises outputting the memory access command to transition a data-clock-enable signal within the memory IC from a deasserted state maintained during the initial portion of the first interval to an asserted state during the latter portion of the first interval.
5. The method of claim 1 wherein outputting the memory access command to enable distribution of the data clock signal within the data interface of the memory IC comprises outputting the memory access command to enable distribution of the data clock signal a predetermined time after the memory access command is received within the memory IC.
6. The method of claim 1 wherein outputting the memory access command comprises outputting a command that specifies a data transfer via the data interface of the memory IC, the method further comprising outputting to the memory IC, during the initial portion of the first interval and prior to outputting the memory access command, a command that instructs the memory IC to perform a first operation without enabling distribution of the data clock signal within the data interface of the memory IC.
7. The method of claim 6 wherein the first operation comprises at least one of a memory refresh operation, a row activation operation or a row precharge operation.
8. The method of claim 1 wherein outputting the memory access command to enable distribution of the data clock signal within the data interface of the memory IC comprises outputting the memory access command to assert a data-clock-enable signal, the method further comprising outputting to the memory IC a data clock control command that instructs the memory IC to set the data-clock-enable signal to a predetermined state.
9. The method of claim 1 wherein outputting the memory access command comprises outputting the memory access command synchronously with respect to the command/address clock signal during assertion of a clock-enable signal at a clock-enable input of the memory IC.
10. The method of claim 1 wherein the data clock signal toggles at the second frequency continuously throughout the first interval.
11. An integrated-circuit memory control component (“memory control IC”) comprising:
a first clock output to output to an integrated-circuit memory component (“memory IC”) a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
a second clock output to output to the memory IC a data clock signal that toggles at a second frequency at least twice the first frequency; and
a command/address interface to output, to the memory IC during an initial portion of the first interval while distribution of the data clock signal within a data interface of the memory IC is disabled, a memory access command synchronously with respect to the command/address clock signal to enable distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval.
12. The memory control IC of claim 11 wherein the command/address interface to output the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises circuitry that outputs the memory access command to enable execution, within the data interface of the memory IC, of either a write data reception operation specified by the memory access command or a read data transmission operation specified by the memory access command.
13. The memory control IC of claim 11 wherein the command/address interface to output the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises circuitry that outputs the memory access command to enable conduction of the data clock signal to timing inputs of at least one of data reception circuitry or data transmission circuitry within the data interface of the memory IC.
14. The memory control IC of claim 11 wherein the command/address interface to output the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises circuitry that outputs the memory access command to transition a data-clock-enable signal within the memory IC from a deasserted state maintained during the initial portion of the first interval to an asserted state during the latter portion of the first interval.
15. The memory control IC of claim 11 wherein the command/address interface to output the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises circuitry that outputs the memory access command to enable distribution of the data clock signal a predetermined time after the memory access command is received within the memory IC.
16. The memory control IC of claim 11 wherein the command/address interface to output the memory access command comprises circuitry to output a command that specifies a data transfer via the data interface of the memory IC, and wherein the command/address interface further outputs to the memory IC, during the initial portion of the first interval and prior to outputting the memory access command, a command that instructs the memory IC to perform a first operation without enabling distribution of the data clock signal within the data interface of the memory IC.
17. The memory control IC of claim 11 wherein the command/address interface to output the memory access command to enable distribution of the data clock within the data interface of the memory IC comprises circuitry that outputs the memory access command to assert a data-clock-enable signal, and wherein the command/address interface further outputs to the memory IC a data clock control command that instructs the memory IC to set the data-clock-enable signal to a predetermined state.
18. The memory control IC of claim 11 wherein the command/address interface to output the memory access command comprises circuitry to output the memory access command synchronously with respect to the command/address clock signal during assertion of a clock-enable signal at a clock-enable input of the memory IC.
19. The memory control IC of claim 11 wherein the data clock signal toggles at the second frequency continuously throughout the first interval.
20. An integrated-circuit memory control component comprising:
means for outputting, to a first clock input of a memory component, a command/address clock signal that toggles continuously throughout a first interval at a first frequency;
means for outputting, to a second clock input of the memory component, a data clock signal that toggles at a second frequency at least twice the first frequency; and
means for outputting, during an initial portion of the first interval while distribution of the data clock signal within a data interface of the memory IC is disabled, a memory access command to the memory IC synchronously with respect to the command/address clock signal to enable distribution of the data clock signal within the data interface of the memory IC during a latter portion of the first interval.