Power amplifier modules with flip-chip and non-flip-chip power transistor dies

1. An amplifier module comprising:

a module substrate having a mounting surface and a plurality of conductive features at the mounting surface;

a first power transistor die coupled to the mounting surface, wherein the first power transistor die has first and second input/output (I/O) contact pads and a first ground contact pad, wherein the first and second I/O pads and the first ground contact pad all are exposed at a first surface of the first power transistor die that faces toward the mounting surface of the module substrate; and

a second power transistor die coupled to the mounting surface, wherein the second power transistor die has third and fourth I/O contact pads and a second ground contact pad, wherein the third and fourth I/O contact pads are exposed at a first surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a second surface of the second power transistor die that faces toward the mounting surface of the module substrate.

2. The amplifier module of claim 1 , wherein the first and second I/O contact pads are electrically coupled to first and second conductive features at the mounting surface, and the first ground contact pad is coupled to a third conductive feature exposed at the mounting surface.

3. The amplifier module of claim 2 , further comprising:

a first wirebond with a first end coupled to a fourth conductive feature at the mounting surface, and a second end coupled to the third I/O contact pad; and

a second wirebond with a first end coupled to a fifth conductive feature at the mounting surface, and a second end coupled to the fourth I/O contact pad.

4. The amplifier module of claim 2 , wherein:

the first and second conductive features are conductive traces at the mounting surface; and

the third conductive feature extends between the mounting surface and a bottom surface of the module substrate.

5. The amplifier module of claim 1 , wherein:

the first power transistor die includes one or more field effect transistors with a first gate structure, a first drain region, and a first source region;

the first I/O contact pad is electrically coupled to the first gate structure;

the second I/O contact pad is electrically coupled to the first drain structure; and

the first ground contact pad is electrically coupled to the first source region.

6. The amplifier module of claim 5 , wherein:

the second power transistor die includes one or more additional field effect transistors with a second gate structure, a second drain region, and a second source region;

the third I/O contact pad is electrically coupled to the second gate structure;

the fourth I/O contact pad is electrically coupled to the second drain structure; and

the second ground contact pad is electrically coupled to the second source region.

7. The amplifier module of claim 6 , wherein:

the first and second power transistor dies form portions of an amplifier path having an input and an output;

the third I/O contact pad of the second transistor is electrically coupled to the input of the amplifier path;

the fourth I/O contact pad of the second transistor is electrically coupled to the first I/O contact pad of the first transistor; and

the second I/O contact pad of the first transistor is electrically coupled to the output of the amplifier path.

8. The amplifier module of claim 6 , wherein:

the first and second power transistor dies form portions of an amplifier path having an input and an output;

the first I/O contact pad of the first transistor is electrically coupled to the input of the amplifier path;

the second I/O contact pad of the first transistor is electrically coupled to the third I/O contact pad of the second transistor; and

the fourth I/O contact pad of the second transistor is electrically coupled to the output of the amplifier path.

9. The amplifier module of claim 1 , wherein the first power transistor die comprises:

a transistor having an active area formed in a die body, the active area being bounded by an outer periphery;

an interconnect structure formed over a frontside of the die body, the interconnect structure containing patterned electrically conductive material defining first, second, and third contacts, which are electrically coupled to first, second, and third subregions, respectively, within the active area of the transistor; and

a frontside I/O interface formed in an outer portion of the interconnect structure, the frontside I/O interface containing the first and second I/O contact pads and the first ground contact pad, the first I/O contact pad being electrically connected to the first contact, the second I/O contact pad being electrically connected to the second contact, and the first ground contact pad being electrically connected the third contact, wherein the first ground contact pad is positioned at a location overlying the active area of the transistor.

10. The amplifier module of claim 9 , wherein:

the transistor comprises a field effect transistor (FET);

the first, second, and third subregions comprise channel, drain, and source subregions, respectively, within the active area of the FET; and

the first, second, and third contacts comprise gate, drain, and source electrode structures, respectively.

11. The amplifier module of claim 9 , wherein the first and second I/O contact pads are positioned at locations outside the outer periphery of the active area of the transistor.

12. The amplifier module of claim 1 , further comprising electrically conductive connection elements on each of the first and second I/O contact pads and the first ground pad configured for flip-chip bonding to the module substrate.

13. The amplifier module of claim 1 , wherein the first power transistor die does not include source through substrate vias.

14. A Doherty amplifier module comprising:

a module substrate having a mounting surface and a plurality of conductive features at the mounting surface;

a first amplifier path that includes a first input, a first output, and a first power transistor die coupled to the mounting surface, wherein the first power transistor die has a first input/output (I/O) contact pad coupled to the first input, a second I/O contact pad coupled to the first output, and a first ground contact pad, all exposed at a first surface of the first power transistor die that faces toward the mounting surface of the module substrate;

a second amplifier path that includes a second input, a second output, and a second power transistor die coupled to the mounting surface, wherein the second power transistor die has a third I/O contact pad coupled to the second input, a fourth I/O contact pad coupled to the second output, and a second ground contact pad, wherein the third and fourth I/O contact pads are exposed at a first surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a second surface of the second power transistor die that faces toward the mounting surface of the module substrate; and

a combining node is electrically coupled to the first and second outputs of the first and second amplifier paths.

15. The Doherty amplifier module of claim 14 , wherein:

a first amplifier path that includes a third power transistor die coupled in series with the first power transistor die, wherein the third power transistor die includes a fifth I/O contact pad coupled to the first input, a sixth I/O contact pad coupled to the first I/O contact pad of the first power transistor die, and a third ground contact pad, wherein the fifth and sixth I/O contact pads are exposed at a first surface of the third power transistor die that faces away from the mounting surface of the module substrate, and the third ground contact pad is exposed at a second surface of the third power transistor die that faces toward the mounting surface of the module substrate.

16. The Doherty amplifier module of claim 15 , wherein:

a first amplifier path is a peaking amplifier path; and

a second amplifier path is a carrier amplifier path.

17. The Doherty amplifier module of claim 15 , wherein:

a first amplifier path is a carrier amplifier path; and

a second amplifier path is a peaking amplifier path.

18. The Doherty amplifier module of claim 14 , wherein:

a first amplifier path that includes a third power transistor die coupled in series with the first power transistor die, wherein the third power transistor die includes a fifth I/O contact pad coupled to the first input, a sixth I/O contact pad coupled to the first I/O contact pad of the first power transistor die, and a third ground contact pad, wherein the fifth and sixth I/O pads and the third ground contact pad are all exposed at a first surface of the third power transistor die that faces toward the mounting surface of the module substrate.

19. The Doherty amplifier module of claim 18 , wherein:

the second amplifier path that includes a fourth power transistor die coupled in series with the second power transistor die, wherein the fourth power transistor die includes a seventh I/O contact pad coupled to the second input, an eighth I/O contact pad coupled to the third I/O contact pad of the second power transistor die, and a fourth ground contact pad, wherein the sixth and seventh I/O pads and the fourth ground contact pad are all exposed at a first surface of the fourth power transistor die that faces toward the mounting surface of the module substrate.

20. The Doherty amplifier module of claim 14 , further comprising:

a phase shift and impedance inversion element electrically coupled between the first and second outputs of the first and second amplifier paths; and

a power splitter with an input terminal configured to receive an input radio frequency (RF) signal, a first output terminal coupled to the first input of the first amplifier path, and a second output terminal coupled to the first input of the second amplifier path.