Semiconductor devices and methods for manufacturing the same

1. A semiconductor device comprising:

a substrate;

a first interlayer insulating layer on the substrate;

a lower interconnection line in the first interlayer insulating layer;

an etch stop layer on the first interlayer insulating layer and the lower interconnection line;

a second interlayer insulating layer on the etch stop layer; and

an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion extending through the etch stop layer and contacting the lower interconnection line,

wherein the via portion comprises a barrier pattern and a conductive pattern on the barrier pattern,

wherein the barrier pattern comprises:

a first barrier layer between the conductive pattern and the second interlayer insulating layer; and

a second barrier layer between the conductive pattern and the lower interconnection line,

wherein an electrical resistivity of the first barrier layer is greater than an electrical resistivity of the second barrier layer, and

wherein a concentration of nitrogen of the first barrier layer is greater than a concentration of nitrogen of the second barrier layer.

2. The semiconductor device of claim 1 , wherein the concentration of nitrogen of the first barrier layer ranges from 10 at % to 60 at %, and

wherein the concentration of nitrogen of the second barrier layer is less than 5 at %.

3. The semiconductor device of claim 1 , wherein the lower interconnection line includes an upper surface that includes a first portion covered by the etch stop layer and a second portion in contact with the via portion, and

wherein the second portion is lower than the first portion relative to the substrate.

4. The semiconductor device of claim 3 , wherein the upper surface of the lower interconnection line comprises a recess that is defined by the second portion of the upper surface of the lower interconnection line, and

wherein the second barrier layer is in the recess and covers a bottom surface of the first barrier layer.

5. The semiconductor device of claim 3 , wherein the second barrier layer includes a second bottom surface, and

wherein the second bottom surface covers at least 80% of the second portion of the upper surface of the lower interconnection line.

6. The semiconductor device of claim 5 , wherein the first barrier layer includes a first bottom surface covering at least a portion of the second portion of the upper surface of the lower interconnection line, and

wherein the second bottom surface covers a remaining portion of the second portion of the upper surface of the lower interconnection line that the first bottom surface does not cover.

7. The semiconductor device of claim 5 , wherein the first barrier layer includes a first bottom surface that is spaced apart from the second portion of the upper surface of the lower interconnection line.

8. The semiconductor device of claim 1 , wherein the first barrier layer includes a tantalum nitride layer, a titanium nitride layer, and/or a manganese nitride layer, and

wherein the second barrier layer includes tantalum, titanium, tungsten, nickel, cobalt, platinum, and/or graphene.

9. The semiconductor device of claim 1 , wherein the conductive pattern comprises a first conductive layer on the barrier pattern and a second conductive layer on the first conductive layer, and

wherein the first and second conductive layers include different metals and include copper, cobalt, ruthenium, tungsten, molybdenum, aluminum, silver, and/or gold.

10. The semiconductor device of claim 1 , wherein a thickness of the first barrier layer is greater than a thickness of the second barrier layer.