IP Library › Granted Patent US 11,587,887
Granted Patent B2
US 11,587,887 · App. 17/148,572 · Granted Feb 21, 2023

Semiconductor device and manufacturing method thereof

Inventors: Yu-Wei Lin (New Taipei, TW); Chun-Yen Lan (Hsinchu, TW); Tzu-Ting Chou (Hsinchu, TW); Tzu-Shiun Sheu (Hsinchu, TW); Chih-Wei Lin (Hsinchu County, TW); Shih-Peng Tai (Hsinchu County, TW); Wei-Cheng Wu (Hsinchu, TW); Ching-Hua Hsieh (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L23/562H01L21/4853H01L21/4857H01L21/4871H01L23/16H01L23/3672H01L23/5383H01L23/5386H01L23/5389
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,587,887
App. No.
17/148,572
Granted
Feb 21, 2023
Kind
B2
Abstract

A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

Claims (49)

1. A semiconductor device, comprising:

a circuit substrate;

a semiconductor package disposed on the circuit substrate; and

a package frame, disposed over the circuit substrate encircling the semiconductor package,

wherein the semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface,

the package frame leaves exposed at least a portion of the second surface of the semiconductor package, and

the package frame forms a cavity, which the cavity encircles the semiconductor package,

wherein the package frame comprises a roof overlying the cavity and outer flanges extending from the roof towards the circuit substrate, the roof extends on the outer flanges, and the outer flanges delimit a side of the cavity opposite with respect to the semiconductor package,

wherein the package frame further comprises inner flanges encircling the semiconductor package and disposed between the semiconductor package and the outer flanges,

wherein a material of the inner flanges has a lower coefficient of thermal expansion than a material of the outer flanges.

2. The semiconductor device of claim 1 , wherein the roof extends on the semiconductor package at a side opposite with respect to the outer flanges.

3. The semiconductor device of claim 1 , wherein the roof is integrally formed with the outer flanges.

4. The semiconductor device of claim 1 , further comprising a first adhesive disposed between the outer flanges and the circuit substrate, and a second adhesive disposed between the inner flanges and the circuit substrate.

5. The semiconductor device of claim 1 , further comprising an adhesive disposed between the roof and at least one selected from the inner flanges and the outer flanges.

6. The semiconductor device of claim 1 , further comprising a heat exchanger contacting the portion of the second surface of the semiconductor package exposed by the package frame through a thermal interface material.

7. The semiconductor device of claim 1 , further comprising a surface mount device connected to the circuit substrate and disposed within the cavity, whereby the roof overlies the surface mount device.

8. The semiconductor device of claim 1 , wherein the inner flanges extends from the roof towards the circuit substrate,

the inner flanges delimit a side of the cavity opposite with respect to the outer flanges, and

the inner flanges are separated from the semiconductor package by a gap.

9. The semiconductor device of claim 1 , wherein the material of the inner flanges is or includes stainless steel.

10. The semiconductor device of claim 1 , further comprising an alignment mark disposed on the circuit substrate and having a complementary shape with respect to a cut corner of the package frame.

11. A semiconductor device, comprising:

a circuit substrate;

a semiconductor package bonded at a side of a front surface to the circuit substrate and further having a rear surface opposite to the front surface;

outer flanges, attached to the circuit substrate and encircling the semiconductor package;

a roof, disposed at a height over the circuit substrate and having two support points to the circuit substrate, wherein the two support points are disposed at opposite edges of the roof, the outer flanges support the roof at a first support point of the support points, at a side of an outer edge of the roof, and an inner edge of the roof forms an opening exposing the rear surface of the semiconductor package; and

inner flanges, attached to the circuit substrate and disposed between the semiconductor package and the outer flanges and supporting the roof at a second support point of the support points at a side of the inner edge of the roof,

wherein a material of the inner flanges has a lower coefficient of thermal expansion than a material of the outer flanges.

12. The semiconductor device of claim 11 , wherein the roof comprises the same material of the outer flanges, and the roof and the outer flanges are formed as a single piece.

13. The semiconductor device of claim 11 , wherein the inner flanges extends from the roof towards the circuit substrate,

the inner flanges delimit a side of the cavity opposite with respect to the outer flanges, and

the inner flanges are separated from the semiconductor package by a gap.

14. The semiconductor device of claim 11 , wherein the material of the inner flanges is or includes stainless steel.

15. The semiconductor device of claim 11 , further comprising an alignment mark disposed on the circuit substrate and having a complementary shape with respect to a cut corner of the package frame.

16. A manufacturing method of a semiconductor device, comprising:

bonding a semiconductor package to a circuit substrate;

disposing a first adhesive on the circuit substrate, wherein the first adhesive forms a first frame around the semiconductor package; and

adhering a package frame to the circuit substrate, wherein the package frame comprises outer flanges and a roof, the outer flanges are adhered to the first adhesive, and the roof extends on the outer flanges while exposing a central area of a rear surface of the semiconductor package,

wherein the package frame further comprises inner flanges encircling the semiconductor package and disposed between the semiconductor package and the outer flanges,

wherein a material of the inner flanges has a lower coefficient of thennal expansion than a material of the outer flanges.

17. The manufacturing method of claim 16 , wherein adhering the package frame comprises:

adhering the outer flanges to the first adhesive;

disposing a second adhesive on the outer flanges; and

adhering the roof to the second adhesive at one side and to the inner flanges at an opposite side.

18. The manufacturing method of claim 16 , wherein the roof and the outer flanges are integrally formed.

19. The manufacturing method of claim 16 , further comprising bonding a surface mount device to the circuit substrate beside the semiconductor package, wherein the first adhesive is disposed further away from the semiconductor package than the surface mount device, and the roof is disposed so as to extend over the surface mount device.

20. The manufacturing method of claim 16 , further comprising:

disposing additional thermal interface material on the central area of the semiconductor package; and

disposing a heat exchanger on the additional thermal interface material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2021
From: LIN, YU-WEI; LAN, CHUN-YEN; CHOU, TZU-TING; SHEU, TZU-SHIUN; LIN, CHIH-WEI; TAI, SHIH-PENG; WU, WEI-CHENG; HSIEH, CHING-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 055598/0490 →
Continuity (1)
Related Publication 20220223542A1 · Jul 14, 2022
Cited By (1)
US 12,702,056