Multi-layer semiconductor package with stacked passive components

1. A method of making a semiconductor package, comprising:

providing a base layer including a leadframe and a base layer dielectric substrate, the leadframe including a conductive die attach pad;

providing a first layer stacked on the base layer, the first layer including a semiconductor die mounted on the conductive die attach pad and embedded within a dielectric substrate of the first layer, and a first set of metal pillars extending through the dielectric substrate of the first layer;

providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and

providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

2. The method of claim 1 ,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,

wherein the dielectric substrate of the first layer forms vias over the bond pads, and

wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

3. The method of claim 1 ,

wherein the dielectric substrate of the first layer is a first dielectric substrate, the second layer further including a second dielectric substrate,

wherein the passive component is embedded in the second dielectric substrate, and

wherein the second set of metal pillars extend through the second dielectric substrate.

4. The method of claim 1 , wherein the inductor is exposed on an outer surface of the semiconductor package.

5. The method of claim 1 , wherein the first set of metal pillars are electrically coupled to perimeter contacts and interior vias of the leadframe.

6. The method of claim 1 ,

wherein an inactive surface of the semiconductor die is bonded to the conductive die attach pad,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and

wherein the bond pads are electrically coupled to the metal trace.

7. The method of claim 1 ,

wherein the metal trace is a first metal trace,

wherein the first layer further includes a second metal trace over the leadframe, and

wherein the semiconductor die and the first set of metal pillars are adjacent to the second metal trace.

8. The method of claim 5 , wherein the base layer dielectric substrate fills gaps between the conductive die attach pad, perimeter contacts, and interior vias of the leadframe.

9. A method of making a semiconductor package comprising:

providing a base layer including a leadframe and a base layer dielectric substrate filling gaps between conductive elements of the leadframe, the conductive elements including a die attach pad, perimeter contacts, and interior vias;

providing a first layer including a semiconductor die mounted on the die attach pad and embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,

wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the perimeter contact and interior vias of the leadframe;

providing a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and

providing a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,

wherein the inductor is exposed on an outer surface of the semiconductor package.

10. The method of claim 9 ,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,

wherein the second dielectric substrate forms vias over the bond pads, and

wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

11. The method of claim 9 ,

wherein an inactive surface of the semiconductor die is bonded to the die attach pad,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and

wherein the bond pads are electrically coupled to the metal trace.

12. The method of claim 9 ,

wherein the second layer further includes a third dielectric substrate,

wherein the passive component is embedded in the third dielectric substrate, and

wherein the second set of metal pillars extend through the third dielectric substrate.

13. A semiconductor package, comprising:

a base layer including a leadframe and a base layer dielectric substrate, the leadframe including a conductive die attach pad;

a first layer stacked on the base layer, the first layer including a semiconductor die mounted on the conductive die attach pad and embedded within a dielectric substrate of the first laver, and a first set of metal pillars extending through the dielectric substrate of the first layer;

a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and

a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.

14. The semiconductor package of claim 13 ,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,

wherein the dielectric substrate of the first layer forms vias over the bond pads, and

wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

15. The semiconductor package of claim 13 ,

wherein the dielectric substrate of the first layer is a first dielectric substrate, the second layer further including a second dielectric substrate,

wherein the passive component is embedded in the second dielectric substrate, and

wherein the second set of metal pillars extend through the second dielectric substrate.

16. The semiconductor package of claim 13 , wherein the inductor is exposed on an outer surface of the semiconductor package.

17. The semiconductor package of claim 13 , wherein the first set of metal pillars are electrically coupled to perimeter contacts and interior vias of the leadframe.

18. The semiconductor package of claim 13 ,

wherein an inactive surface of the semiconductor die is bonded to the conductive die attach pad,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and

wherein the bond pads are electrically coupled to the metal trace.

19. The semiconductor package of claim 3 ,

wherein the metal trace is a first metal trace,

wherein the first layer further includes a second metal trace over the leadframe, and

wherein the semiconductor die and the first set of metal pillars are adjacent to the second metal trace.

20. The semiconductor package of claim 17 , wherein the base layer dielectric substrate fills between the conductive die attach pad, perimeter contacts, and interior vias of the leadframe.

21. A semiconductor package comprising:

a base layer including a leadframe and a base layer dielectric substrate filling gaps between conductive elements of the leadframe, the conductive elements including a die attach pad, perimeter contacts, and interior vias;

a first layer including a semiconductor die mounted on the die attach pad and embedded within a second dielectric substrate, and a first set of metal pillars extending through the second dielectric substrate,

wherein the first layer is stacked on the base layer such that the first set of metal pillars are electrically coupled to the perimeter contacts and interior vias of the leadframe;

a second layer stacked on the first layer, the second layer including a metal trace patterned on the second dielectric substrate, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer; and

a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars,

wherein the inductor is exposed on an outer surface of the semiconductor package.

22. The semiconductor package of claim 21 ,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die,

wherein the second dielectric substrate forms vias over the bond pads, and

wherein the metal trace fills the vias, electrically connecting the functional circuitry to the metal trace.

23. The semiconductor package of claim 21 ,

wherein an inactive surface of the semiconductor die is bonded to the die attach pad,

wherein the semiconductor die includes bond pads providing electrical connections to functional circuitry of the semiconductor die, and

wherein the bond pads are electrically coupled to the metal trace.

24. The semiconductor package of claim 21 ,

wherein the second layer further includes a third dielectric substrate,

wherein the passive component is embedded in the third dielectric substrate, and

wherein the second set of metal pillars extend through the third dielectric substrate.