IP Library Granted Patent US 11,587,922
Granted Patent B2
US 11,587,922 · App. 17/026,900 · Granted Feb 21, 2023

Process control for package formation

Inventors: Ming-Fa Chen (Taichung, TW); Hsien-Wei Chen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L25/50H01L21/56H01L21/76898H01L23/3114H01L23/3128H01L23/481H01L23/5383H01L24/09H01L24/14H01L24/19H01L24/89H01L25/03H01L25/105H01L23/5389H01L25/0657H01L25/18H01L2224/02331H01L2224/02379H01L2224/04105H01L2224/08145H01L2224/12105H01L2224/16227H01L2224/32145H01L2224/32225H01L2224/73265H01L2224/94H01L2225/0651H01L2225/06541H01L2225/06568H01L2225/1035H01L2225/1058H01L2924/15311H01L2924/3511
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Quick Facts
Patent No.
US 11,587,922
App. No.
17/026,900
Granted
Feb 21, 2023
Kind
B2
Abstract

A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.

Claims (40)

1. A package comprising:

a first device die;

a second device die and a third device die bonded to the first device die;

an isolation region between the second device die and the third device die, wherein the isolation region comprises:

a first etch stop layer having sidewall portions contacting the second and the third device dies and a bottom portion contacting a top surface of the first device die;

a first dielectric layer over the first etch stop layer;

a second etch stop layer over the first dielectric layer; and

a second dielectric layer over the second etch stop layer; and

a through-via penetrating through the isolation region to electrically connect to the first device die.

2. The package of claim 1 , wherein the through-via penetrates through all dielectric layers in the isolation region.

3. The package of claim 1 , wherein the through-via is tapered with upper portions increasingly wider than respective lower portions.

4. The package of claim 1 , wherein the first etch stop layer has a first thickness smaller than a second thickness of the second etch stop layer.

5. The package of claim 1 , wherein the first etch stop layer and the second etch stop layer are formed of a same material.

6. The package of claim 1 , wherein each of the first etch stop layer, the first dielectric layer, and the second etch stop layer is a conformal layer.

7. The package of claim 6 , wherein the second dielectric layer is a non-conformal layer.

8. The package of claim 1 , wherein the first dielectric layer is formed of a material different from materials of the first etch stop layer and the second etch stop layer.

9. The package of claim 8 , wherein the second etch stop layer is formed of an additional material different from materials of the first dielectric layer and the second dielectric layer.

10. A package comprising:

a first package component;

a second package component over the first package component; and

an isolation region encircling the second package component, wherein the isolation region comprises:

a first plurality of layers formed of a first material; and

a second plurality of layers formed of a second material different from the first material, wherein each of the second plurality of layers overlaps a corresponding one of the first plurality of layers.

11. The package of claim 10 , wherein the first plurality of layers comprise silicon nitride, and the second plurality of layers comprise silicon oxide.

12. The package of claim 10 , wherein the isolation region is over, and contacting, the first package component.

13. The package of claim 10 further comprising a through-via penetrating through the first plurality of layers and the second plurality of layers to electrically connect to the first package component.

14. The package of claim 10 , wherein the first package component comprises an interposer, and the second package component comprises a device die.

15. The package of claim 10 , wherein a bottom layer in the first plurality of layers comprises a horizontal portion in physical contact with a top surface of the first package component, and a vertical portion in physical contact with a sidewall of the second package component.

16. The package of claim 10 , wherein the first plurality of layers and the second plurality of layers are allocated alternatingly.

17. A package comprising:

a first package component, wherein the first package component comprises an electrical connector;

a second package component and a third package component over and bonding to the first package component;

an isolation region over the first package component, wherein the isolation region is between the second package component and the third package component, and wherein the isolation region comprises:

a first layer;

a second layer over the first layer; and

a third layer over the second layer, wherein the first layer and the third layer are formed of a same dielectric material; and

a conductive feature penetrating through the isolation region to electrically connect to the electrical connector of the first package component.

18. The package of claim 17 , wherein the isolation region further comprises a dielectric region filling rest of a gap between the second package component and the third package component, wherein the dielectric region is directly over a bottom portion of the third layer.

19. The package of claim 17 further comprising a redistribution line over the second package component and the third package component, wherein the redistribution line is electrically connected to the conductive feature.

20. The package of claim 17 , wherein the first layer is thinner than the third layer.

Continuity (3)
Division 16121861 · Sep 5, 2018
Provisional Application 62586305 · Nov 15, 2017
Related Publication 20210005595A1 · Jan 7, 2021