Field effect transistor including gate insulating layer formed of two-dimensional material

1. A field effect transistor comprising:

a first channel layer;

a second channel layer on the first channel layer;

a gate insulating layer including an insulative, high-k, two-dimensional material on the second channel layer;

a gate electrode on the gate insulating layer;

a first electrode electrically connected to the first channel layer; and

a second electrode electrically connected to the second channel layer,

wherein each of the first channel layer and the second channel layer comprises a semiconductor material having a two-dimensional crystal structure,

wherein the gate insulating layer comprises a ferroelectric material having a two-dimensional crystal structure,

wherein an interface charge density between the second channel layer and the gate insulating layer is 1×10 12 per cm 2 or less, and

wherein the field effect transistor has a subthreshold swing value of about 60 mV/dec or less.

2. The field effect transistor of claim 1 , wherein the insulative, high-k, two-dimensional material has a dielectric constant of about 10 or more.

3. The field effect transistor of claim 1 , wherein the ferroelectric material having the two-dimensional crystal structure comprises at least one of In 2 Se 2 , HfZrO 2 , and Si—HfO 2 .

4. The field effect transistor of claim 1 , wherein the insulative, high-k, two-dimensional material comprises at least one of 1T-HfO 2 , 1T-ZrO 2 , 1T-GeO 2 , 1T-SnO 2 , 1T-TiO 2 , 1T-PtO 2 , 2H-GeO 2 , 2H-HfO 2 , 1T-HfS 2 , 1T-PdO 2 , 2H-ZrO 2 , 1T-PtS 2 , 2H-MoO 2 , 2H-WO 2 , and 1T-SnS 2 .

5. The field effect transistor of claim 1 , wherein the semiconductor material having the two-dimensional crystal structure comprises at least one of graphene, black phosphorus, phosphorene, and a transition metal dichalcogenide.

6. The field effect transistor of claim 1 , wherein the semiconductor material having the two-dimensional crystal structure comprises at least one of graphene, black phosphorus, phosphorene, MoS 2 , WS 2 , TaS 2 , HfS 2 , ReS 2 , TiS 2 , NbS 2 , SnS 2 , MoSe 2 , WSe 2 , TaSe 2 , HfSe 2 , ReSe 2 , TiSe 2 , NbSe 2 , SnSe 2 , MoTe 2 , WTe 2 , TaTe 2 , HfTe 2 , ReTe 2 , TiTe 2 , NbTe 2 , and SnTe 2 .

7. The field effect transistor of claim 1 , wherein

the second channel layer and the gate insulating layer are van-der-Waals bonded to each other.

8. The field effect transistor of claim 1 , wherein the first channel layer and the second channel layer have energy bands different from each other.

9. The field effect transistor of claim 8 , wherein the first channel layer and the second channel layer comprise different semiconductor materials and are doped to have an electrically identical conductivity type.

10. The field effect transistor of claim 8 , wherein the first channel layer is doped to have a first conductivity type, and the second channel layer is doped to have a second conductivity type which is electrically opposite to the first conductivity type.

11. The field effect transistor of claim 10 , wherein the first channel layer and the second channel layer comprise a same semiconductor material.

12. The field effect transistor of claim 10 , wherein the first channel layer and the second channel layer comprise different semiconductor materials.

13. The field effect transistor of claim 8 , wherein the field effect transistor is a tunneling field effect transistor.

14. The field effect transistor of claim 1 , wherein the gate insulating layer is disposed to cover a portion of an upper surface of the second channel layer.

15. The field effect transistor of claim 1 , wherein the gate insulating layer and the gate electrode protrude in a lateral direction toward the first electrode from a first edge of the second channel layer such that the gate insulating layer and the gate electrode extend onto an upper surface of the first electrode.

16. The field effect transistor of claim 1 , wherein the gate insulating layer and the gate electrode are disposed to protrude in a lateral direction toward the second electrode from a second edge of the second channel layer such that the gate insulating layer and the gate electrode extend onto an upper surface of the second electrode.

17. The field effect transistor of claim 1 , further comprising an insulator layer disposed between the first channel layer and the second channel layer.

18. The field effect transistor of claim 17 , wherein the insulator layer has a thickness of about 1 nm to about 5 nm.

19. The field effect transistor of claim 17 , wherein

the insulator layer covers an entire upper surface of the first channel layer, and

the second channel layer covers a portion of an upper surface of the insulator layer.

20. The field effect transistor of claim 19 , wherein the insulator layer and the second channel layer protrude in a lateral direction toward the second electrode from an edge of the first channel layer.

21. The field effect transistor of claim 1 , further comprising:

a substrate which is insulative,

wherein the first channel layer is disposed on an upper surface of the substrate.

22. The field effect transistor of claim 21 , wherein

the second channel layer covers a portion of an upper surface of the first channel layer,

a portion of the second channel layer protrudes in a lateral direction toward the second electrode from an edge of the first channel layer, and

the portion of the second channel layer protruding towards the second electrode is spaced apart from the substrate.

23. The field effect transistor of claim 21 , wherein

the second channel layer covers a portion of an upper surface of the first channel layer,

a portion of the second channel layer protrudes in a lateral direction toward the second electrode from an edge of the first channel layer, and

the portion of the second channel layer protruding towards the second electrode contacts the upper surface of the substrate.

24. The field effect transistor of claim 21 , further comprising:

a first contact layer on the substrate in direct contact with the first channel layer; and

a second contact layer on the substrate in direct contact with the second channel layer.

25. The field effect transistor of claim 24 , wherein

the first electrode is on the first contact layer, and

the second electrode is on the second contact layer.

26. The field effect transistor of claim 21 , further comprising:

a lower gate insulating layer embedded in the substrate and contacting with a lower surface of the first channel layer; and

a lower gate electrode embedded in the substrate and contacting with a lower surface of the lower gate insulating layer,

wherein the lower gate insulating layer comprises an insulative, high-k, two-dimensional material.