Resistive memory with vertical transport transistor

1. A memory cell, comprising:

a vertically-oriented fin;

a resistive memory device located on a first lateral side of the fin below a top of the fin, wherein the resistive memory device comprises a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode; and

a vertical field-effect transistor (FET) comprising:

a metal gate; and

a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.

2. The memory cell of claim 1 , wherein the gate dielectric comprises a gate material, and wherein the gate material is different than the resistive element.

3. The memory cell of claim 1 , comprising a top source/drain (S/D) at a top of the fin and a bottom source/drain (S/D) at a bottom of the fin, wherein the bottom source/drain is electrically connected to the bottom electrode.

4. The memory cell of claim 3 , comprising a bottom spacer located between the gate dielectric and the bottom S/D.

5. The memory cell of claim 1 , comprising a vertical spacer located between the fin and the bottom electrode.

6. The memory cell of claim 5 , wherein the vertical spacer and the bottom electrode extend vertically down beyond a bottom of the fin.

7. The memory cell of claim 1 , comprising a top spacer located above the vertical FET and the resistive memory device.

8. The memory cell of claim 1 , wherein a material of the resistive element differs from a material of the gate dielectric only in an atomic concentration.

9. A method of fabricating a memory cell, comprising:

forming a channel layer on a doped bottom source/drain (S/D) layer;

etching a portion of the undoped channel layer to form a fin;

forming a resistive memory device on a first lateral side of the fin;

forming a gate dielectric contacting a second lateral side of the fin; and

forming a metal gate contacting the gate dielectric.

10. The method of claim 9 , wherein forming the resistive memory device comprises forming a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode.

11. The method of claim 10 , comprising forming a vertical spacer between the bottom electrode and the first lateral side of the fin.

12. The method of claim 9 , wherein etching a portion of the channel layer comprises etching vertically into the doped bottom S/D layer.

13. The method of claim 9 , comprising forming a bottom spacer located between the gate dielectric and the doped bottom S/D layer.

14. The method of claim 9 , comprising forming a top spacer on the metal gate, the gate dielectric, and the resistive memory device.

15. A memory cell, comprising:

a fin oriented vertically between a top source/drain (S/D) layer and a bottom S/D layer;

a resistive memory device located on a first lateral side of the fin below a top of the fin comprising a bottom electrode electrically contacting the bottom S/D layer;

a field-effect transistor (FET) comprising a gate conductor and a gate dielectric contacting a second lateral side of the fin.

16. The memory cell of claim 15 , comprising:

a word line electrically connected to the gate conductor of the FET;

a bit line electrically connected to the top S/D layer; and

a source line electrically connected to a top electrode of the resistive memory device.

17. The memory cell of claim 15 , comprising a bottom spacer located between the gate conductor and the bottom S/D.

18. The memory cell of claim 15 , comprising a vertical spacer located between the fin and the bottom electrode.

19. The memory cell of claim 18 , wherein the vertical spacer and the bottom electrode extend vertically down beyond a bottom of the fin.

20. The memory cell of claim 17 , wherein the resistive memory device comprises a resistive element having a material that differs from a material of the gate dielectric only in an atomic concentration.