IP Library › Granted Patent US 11,588,666
Granted Patent B2
US 11,588,666 · App. 17/352,498 · Granted Feb 21, 2023

Signal transmission system, transmitter encoding apparatus and receiver decoding apparatus

Inventors: Hsu-Jung Tung (Hsinchu, TW); Lien-Hsiang Sung (Hsinchu, TW)
Assignee: REALTEK SEMICONDUCTOR CORPORATION
H04L25/0272H04J13/0011H04J13/102
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Quick Facts
Patent No.
US 11,588,666
App. No.
17/352,498
Granted
Feb 21, 2023
Kind
B2
Abstract

A transmitter encoding apparatus includes a multiplexer and a first transmitter encoder. The multiplexer receives a first digital signal and a second signal and to generate an output, in which the output of the multiplexer includes M-bit code words of the first digital signal and M-bit code words of the second digital signal arranged in an interleaved manner. The first transmitter encoder receives the output of the multiplexer and generates N-bit code words, and N is not equal to M. The first transmitter encoder determines a current N-bit code word of the N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the N-bit code words. The first transmitter encoder transmits the N-bit code words to a receiver decoding apparatus including a demultiplexer and a first receiver decoder configured to decode the N-bit code words.

Claims (25)

1. A signal transmission system, comprising:

a transmitter encoding apparatus comprising:

a multiplexer, configured to receive a first digital signal and a second digital signal and generate an output, wherein the output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal, wherein the plurality of M-bit code words of the first digital signal and the plurality of M-bit code words of the second digital signal are arranged in an interleaved manner, and M is a positive integer; and

a first transmitter encoder, configured to encode the output of the multiplexer to generate a plurality of N-bit code words, wherein N is a positive integer and N is not equal to M, wherein the first transmitter encoder is configured to determine a current N-bit code word of the plurality of N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the plurality of N-bit code words;

a receiver decoding apparatus, coupled to the transmitter encoding apparatus, comprising:

a first receiver decoder, configured to decode the plurality of N-bit code words to generate a plurality of I-bit code words, wherein I is a positive integer and I is not equal to N; and

a demultiplexer, configured to alternately deinterleave and assign the plurality of I-bit code words to a plurality of output terminals of the demultiplexer;

a second transmitter encoder, configured to output the first digital signal and the second digital signal, wherein the plurality of M-bit code words of the first digital signal and the plurality of M-bit code words of the second digital signal both have substantially identical numbers of ones and zeros; and

a second receiver decoder, configured to decode outputs of the output terminals of the demultiplexer.

2. The signal transmission system of claim 1 , wherein if an arbitrary N-bit code word of the plurality of N-bit code words has a positive disparity, an arbitrary N-bit code word of the plurality of N-bit code words with a negative disparity is adjacent to the arbitrary N-bit code word with the positive disparity.

3. The signal transmission system of claim 1 , wherein the plurality of N-bit code words have substantially identical numbers of ones and zeros.

4. A transmitter encoding apparatus, comprising:

a multiplexer, configured to receive a first digital signal and a second digital signal and generate an output, wherein the output of the multiplexer comprises a plurality of M-bit code words of the first digital signal and a plurality of M-bit code words of the second digital signal, wherein the plurality of M-bit code words of the first digital signal and the plurality of M-bit code words of the second digital signal are arranged in an interleaved manner, and M is a positive integer;

a first transmitter encoder, configured to receive the output of the multiplexer and to generate a plurality of N-bit code words, wherein N is a positive integer and N is not equal to M, wherein a first transmitter encoder is configured to determine a current N-bit code word of the plurality of N-bit code words according to the output of the multiplexer and a disparity of a previous N-bit code word of the plurality of N-bit code words;

a second transmitter encoder, configured to output a third digital signal and a fourth digital signal, wherein a plurality of K-bit code words of the third digital signal and a plurality of K-bit code words of the fourth digital signal both have substantially identical numbers of ones and zeros, wherein K is a positive integer and K is not equal to M; and

a first transmitter decoder, configured to decode the third digital signal and the fourth digital signal to generate the first digital signal and the second digital signal respectively,

wherein the first transmitter encoder is configured to transmit the plurality of N-bit code words to a receiver decoding apparatus comprising a demultiplexer and a first receiver decoder configured to decode the plurality of N-bit code words.

5. The transmitter encoding apparatus of claim 4 , wherein if an arbitrary N-bit code word of the plurality of N-bit code words has a positive disparity, an arbitrary N-bit code word of the plurality of N-bit code words with a negative disparity is adjacent to the arbitrary N-bit code word with the positive disparity.

6. The transmitter encoding apparatus of claim 4 , wherein the plurality of N-bit code words have substantially identical numbers of ones and zeros.

7. The transmitter encoding apparatus of claim 4 , wherein an encoding algorithm of the second transmitter encoder is an M-bit to K-bit encoding algorithm, and a decoding algorithm of the first transmitter decoder is a K-bit to M-bit decoding algorithm.

8. A receiver decoding apparatus, comprising:

a first receiver decoder, configured to decode a plurality of N-bit code words to generate a plurality of I-bit code words, wherein the plurality of N-bit code words have substantially identical numbers of ones and zeros, wherein N and I are both positive integers and N is not equal to I;

a demultiplexer, configured to alternately deinterleave and assign the plurality of I-bit code words to a plurality of output terminals of the demultiplexer, wherein the first receiver decoder is configured to receive the plurality of N-bit code words from a transmitter encoding apparatus comprising a multiplexer and a first transmitter encoder configured to generate the plurality of N-bit code words; and

a second receiver decoder, wherein the second receiver decoder is configured to decode a plurality of outputs of the output terminals of the demultiplexer.

9. The receiver decoding apparatus of claim 8 , wherein if an arbitrary N-bit code word of the plurality of N-bit code words has a positive disparity, an arbitrary N-bit code word of the plurality of N-bit code words with a negative disparity is adjacent to the arbitrary N-bit code word with the positive disparity.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2021
From: TUNG, HSU-JUNG; SUNG, LIEN-HSIANG
To: REALTEK SEMICONDUCTOR CORPORATION
Reel/Frame 056598/0843 →
Priority Claims (1)
TW 110104819 · Feb 8, 2021 · national
Continuity (2)
Provisional Application 63081994 · Sep 23, 2020
Related Publication 20220094575A1 · Mar 24, 2022
Cited By (1)
US 12,640,812