IP Library › Granted Patent US 11,592,859

Granted Patent B2

US 11,592,859 · App. 17/206,784 · Granted Feb 28, 2023

Gate clock generator and display device

Inventors: Siduk Sung (Hwaseong-si, KR); Dae-Sik Lee (Hwaseong-si, KR); Sanghyun Lee (Seongnam-si, KR)

Assignee: SAMSUNG DISPLAY CO., LTD.

G06F1/08 G06F1/10 G09G3/20 G09G2310/08 G09G2330/028

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Quick Facts

Patent No.: US 11,592,859
App. No.: 17/206,784
Granted: Feb 28, 2023
Kind: B2

External Links

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Abstract

A gate clock generator of a display device includes a carry clock generator configured to sequentially generate N carry clock signals based on a carry-on clock signal and a carry-off clock signal, a scan clock generator configured to generate N scan clock signals based on a scan-on clock signal and a scan-off clock signal, and a sensing clock generator configured to generate N sensing clock signals based on a sensing-on clock signal and a sensing-off clock signal. In a multi-clock mode of the display device, during an on period of a K-th carry clock signal, the scan clock generator outputs a K-th scan clock signal such that the K-th scan clock signal has a number of pulses that corresponds to a number of pulses of the scan-on clock signal in the on period of the K-th carry clock signal, and the sensing clock generator outputs a K-th sensing clock signal such that the K-th sensing clock signal has a number of pulses that corresponds to a number of pulses of the sensing-on clock signal in the on period of the K-th carry clock signal.

Claims (68)

1. A gate clock generator of a display device, comprising:

a carry clock generator configured to sequentially generate N carry clock signals based on a carry-on clock signal and a carry-off clock signal, where N is an integer greater than 1;

a scan clock generator configured to generate N scan clock signals based on a scan-on clock signal and a scan-off clock signal; and

a sensing clock generator configured to generate N sensing clock signals based on a sensing-on clock signal and a sensing-off clock signal,

wherein, in a multi-clock mode of the display device, during an on period of a K-th carry clock signal of the N carry clock signals, where K is an integer greater than 0 and less than or equal to N, the scan clock generator outputs a K-th scan clock signal of the N scan clock signals such that the K-th scan clock signal has a number of pulses that corresponds to a number of pulses of the scan-on clock signal in the on period of the K-th carry clock signal, and the sensing clock generator outputs a K-th sensing clock signal of the N sensing clock signals such that the K-th sensing clock signal has a number of pulses that corresponds to a number of pulses of the sensing-on clock signal in the on period of the K-th carry clock signal.

2. The gate clock generator of claim 1 , wherein, in the multi-clock mode, the carry clock generator provides the N carry clock signals to the scan clock generator and the sensing clock generator.

3. The gate clock generator of claim 2 , wherein, in the multi-clock mode, during the on period of the K-th carry clock signal, the scan clock generator changes the K-th scan clock signal to an on level in response to each pulse of the scan-on clock signal, and changes the K-th scan clock signal to an off level in response to each pulse of the scan-off clock signal, and

wherein, in the multi-clock mode, during the on period of the K-th carry clock signal, the sensing clock generator changes the K-th sensing clock signal to the on level in response to each pulse of the sensing-on clock signal, and changes the K-th sensing clock signal to the off level in response to each pulse of the sensing-off clock signal.

4. The gate clock generator of claim 1 , wherein the carry clock generator includes:

a carry mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a carry pulse generator block configured to sequentially generate the N carry clock signals based on the carry-on clock signal and the carry-off clock signal, and to provide the N carry clock signals to the scan clock generator and the sensing clock generator in response to the mode signal indicating the multi-clock mode; and

a carry level shifter block configured to adjust voltage levels of the N carry clock signals to voltage levels suitable for a gate driver, and to provide the N carry clock signals to the gate driver.

5. The gate clock generator of claim 1 , wherein the scan clock generator includes:

a scan mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a scan pulse generator block configured to generate the N scan clock signals based on the N carry clock signals, the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N scan clock signals based on the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

a scan level shifter block configured to adjust voltage levels of the N scan clock signals to voltage levels suitable for a gate driver, and to provide the N scan clock signals to the gate driver.

6. The gate clock generator of claim 1 , wherein the sensing clock generator includes:

a sensing mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a sensing pulse generator block configured to generate the N sensing clock signals based on the N carry clock signals, the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

a sensing level shifter block configured to adjust voltage levels of the N sensing clock signals to voltage levels suitable for a gate driver, and to provide the N scan clock signals to the gate driver.

7. The gate clock generator of claim 1 , wherein, in the multi-clock mode, the carry clock generator provides a multi sensing enable signal to the scan clock generator and the sensing clock generator.

8. The gate clock generator of claim 7 , wherein, in the multi-clock mode, during a first on period of the multi sensing enable signal, the scan clock generator changes a first scan clock signal of the N scan clock signals to an on level in response to each pulse of the scan-on clock signal, and changes the first scan clock signal to an off level in response to each pulse of the scan-off clock signal,

wherein, in the multi-clock mode, during a second on period of the multi sensing enable signal, the scan clock generator changes a second scan clock signal of the N scan clock signals to the on level in response to each pulse of the scan-on clock signal, and changes the second scan clock signal to the off level in response to each pulse of the scan-off clock signal,

wherein, in the multi-clock mode, during the first on period of the multi sensing enable signal, the sensing clock generator changes a first sensing clock signal of the N sensing clock signals to the on level in response to each pulse of the sensing-on clock signal, and changes the first sensing clock signal to the off level in response to each pulse of the sensing-off clock signal, and

wherein, in the multi-clock mode, during the second on period of the multi sensing enable signal, the sensing clock generator changes a second sensing clock signal of the N sensing clock signals to the on level in response to each pulse of the sensing-on clock signal, and changes the second sensing clock signal to the off level in response to each pulse of the sensing-off clock signal.

9. The gate clock generator of claim 1 , wherein the carry clock generator includes:

a carry mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a carry pulse generator block configured to sequentially generate the N carry clock signals based on the carry-on clock signal and the carry-off clock signal, and to generate a multi sensing enable signal in response to the mode signal indicating the multi-clock mode, the multi sensing enable signal having an on period when at least one of the N carry clock signals has an on period; and

a carry level shifter block configured to adjust voltage levels of the N carry clock signals to voltage levels suitable for a gate driver, and to provide the N carry clock signals to the gate driver.

10. The gate clock generator of claim 1 , wherein the scan clock generator includes:

a scan mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a scan pulse generator block configured to generate the N scan clock signals based on a multi sensing enable signal received from the carry clock generator, the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N scan clock signals based on the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

a scan level shifter block configured to adjust voltage levels of the N scan clock signals to voltage levels suitable for a gate driver, and to provide the N scan clock signals to the gate driver.

11. The gate clock generator of claim 1 , wherein the sensing clock generator includes:

a sensing mode selection block configured to determine an operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a sensing pulse generator block configured to generate the N sensing clock signals based on a multi sensing enable signal received from the carry clock generator, the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

12. A gate clock generator of a display device comprising:

a carry clock generator configured to receive a carry-on clock signal, a carry-off clock signal from a controller of the display device, and to sequentially generate N carry clock signals based on the carry-on clock signal and the carry-off clock signal, where N is an integer greater than 1;

a scan clock generator configured to receive a multi sensing enable signal, a scan-on clock signal and a scan-off clock signal from the controller, to generate N scan clock signals based on the multi sensing enable signal, the scan-on clock signal and the scan-off clock signal in a multi-clock mode of the display device, and to generate the N scan clock signals based on the scan-on clock signal and the scan-off clock signal in an operation mode other than the multi-clock mode; and

a sensing clock generator configured to receive the multi sensing enable signal, a sensing-on clock signal and a sensing-off clock signal from the controller, to generate N sensing clock signals based on the multi sensing enable signal, the sensing-on clock signal and the sensing-off clock signal in the multi-clock mode, and to generate the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal in the operation mode other than the multi-clock mode.

13. The gate clock generator of claim 12 , wherein, in the multi-clock mode, during a first on period of the multi sensing enable signal, the scan clock generator changes a first scan clock signal of the N scan clock signals to an on level in response to each pulse of the scan-on clock signal, and changes the first scan clock signal to an off level in response to each pulse of the scan-off clock signal,

14. The gate clock generator of claim 12 , wherein the scan clock generator includes:

a scan mode selection block configured to determine the operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a scan pulse generator block configured to generate the N scan clock signals based on the multi sensing enable signal received from the controller, the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N scan clock signals based on the scan-on clock signal and the scan-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

a scan level shifter block configured to adjust voltage levels of the N scan clock signals to voltage levels suitable for a gate driver, and to provide the N scan clock signals to the gate driver.

15. The gate clock generator of claim 12 , wherein the sensing clock generator includes:

a sensing mode selection block configured to determine the operation mode of the gate clock generator, and to generate a mode signal representing the operation mode;

a sensing pulse generator block configured to generate the N sensing clock signals based on the multi sensing enable signal received from the controller, the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the multi-clock mode, and to generate the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal in response to the mode signal indicating the operation mode other than the multi-clock mode; and

16. A display device comprising:

a display panel including a plurality of pixels;

a data driver coupled to the plurality of pixels through a plurality of data lines;

a sensing circuit coupled to the plurality of pixels through a plurality of sensing lines;

a controller configured to control the data driver and the sensing circuit, and to generate a carry-on clock signal, a carry-off clock signal, a scan-on clock signal, a scan-off clock signal, a sensing-on clock signal and a sensing-off clock signal;

a gate clock generator configured to sequentially generate N carry clock signals based on the carry-on clock signal and the carry-off clock signal, to generate N scan clock signals based on the scan-on clock signal and the scan-off clock signal, and to generate N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal, where N is an integer greater than 1; and

a gate driver configured to provide a plurality of scan signals and a plurality of sensing signals to the plurality of pixels based on the N carry clock signals, the N scan clock signals and the N sensing clock signals,

17. The display device of claim 16 , wherein the gate clock generator includes:

a carry clock generator configured to sequentially generate the N carry clock signals based on the carry-on clock signal and the carry-off clock signal;

a scan clock generator configured to generate the N scan clock signals based on the scan-on clock signal and the scan-off clock signal; and

a sensing clock generator configured to generate the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal.

18. The display device of claim 17 , wherein, in the multi-clock mode, the carry clock generator provides the N carry clock signals to the scan clock generator and the sensing clock generator.

19. The display device of claim 17 , wherein, in the multi-clock mode, the carry clock generator provides a multi sensing enable signal to the scan clock generator and the sensing clock generator.

20. The display device of claim 17 , wherein, in the multi-clock mode, the controller provides a multi sensing enable signal to the scan clock generator and the sensing clock generator.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2021

From: SUNG, SIDUK; LEE, DAE-SIK; LEE, SANGHYUN

To: SAMSUNG DISPLAY CO., LTD.

Reel/Frame 055652/0324 →

Priority Claims (1)

KR 10-2020-0086832 · Jul 14, 2020 · national

Continuity (1)

Related Publication 20220019256A1 · Jan 20, 2022