Combining load or store instructions

1. A method for combining load or store instructions, comprising:

identifying, in a processor pipeline, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width, wherein the multiple memory access instructions are one of an assembly code instruction or a compiled code instruction, wherein the at least one pattern of multiple memory access instructions is identified based on an attribute of each of the multiple memory access instructions and the attributes of the multiple memory access instructions are stored in a storage instruction table;

determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line based on the attributes of the multiple memory access instructions stored in the storage instruction table;

determining whether a one equivalent memory access instruction to replace the multiple memory access instructions creates a memory hazard where the one equivalent memory access instruction utilizes more of the available bus width than either of the replaced memory access instructions;

replacing, within the processor pipeline, the multiple memory access instructions with the one equivalent memory access instruction when the one equivalent memory access instruction does not create the memory hazard; and

updating the storage instruction table to track the multiple memory access instructions replaced with the one equivalent memory access instruction.

2. The method recited in claim 1 , wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to determining that the multiple memory access instructions appear consecutively in the processor pipeline and target the adjacent memory at contiguous offsets.

3. The method recited in claim 2 , wherein the multiple memory access instructions target the adjacent memory at contiguous positive offsets.

4. The method recited in claim 2 , wherein the multiple memory access instructions target the adjacent memory at contiguous negative offsets.

5. The method recited in claim 1 , wherein the multiple memory access instructions utilize different portions of the available bus width.

6. The method recited in claim 1 , further comprising determining that the multiple memory access instructions target the adjacent memory in response to the multiple memory access instructions including a first memory access instruction that alters a value stored in the common base register and a second memory access that accesses memory at a location adjacent to the altered value stored in the common base register.

7. The method recited in claim 1 , further comprising determining that the multiple memory access instructions appear non-consecutively in the processor pipeline, wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to determining that no intervening store instructions appear between the non-consecutive memory access instructions.

8. The method recited in claim 1 , further comprising determining that the multiple memory access instructions appear non-consecutively in the processor pipeline, wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to determining that one or more intervening store instructions appearing between the non-consecutive memory access instructions use the common base register referenced in the multiple memory access instructions and that there are no overlapping bytes between the non-consecutive memory access instructions and the one or more intervening store instructions.

9. The method recited in claim 1 , wherein the multiple memory access instructions comprise multiple dynamic instances of the same memory access instruction.

10. The method recited in claim 1 , wherein the multiple memory access instructions comprise multiple load instructions or multiple store instructions.

11. An apparatus, comprising:

a processor configured to identify, in a pipeline associated with the processor, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width, wherein the multiple memory access instructions are one of an assembly code instruction or a compiled code instruction, wherein the at least one pattern of multiple memory access instructions is identified based on an attribute of each of the multiple memory access instructions and the attributes of the multiple memory access instructions are stored in a storage instruction table, determine that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line based on the attributes of the multiple memory access instructions stored in the storage instruction table, determine whether a one equivalent memory access instruction to replace the multiple memory access instructions creates a memory hazard where the one equivalent memory access instruction utilizes more of the available bus width than either of the replaced memory access instructions, replace, within the pipeline associated with the processor, the multiple memory access instructions with the one equivalent memory access instruction when the one equivalent memory access instruction does not create the memory hazard, and update the storage instruction table to track the multiple memory access instructions replaced with the one equivalent memory access instruction.

12. The apparatus recited in claim 11 , wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to the multiple memory access instructions appearing consecutively in the pipeline and targeting the adjacent memory at contiguous offsets.

13. The apparatus recited in claim 12 , wherein the multiple memory access instructions target the adjacent memory at contiguous positive offsets.

14. The apparatus recited in claim 12 , wherein the multiple memory access instructions target the adjacent memory at contiguous negative offsets.

15. The apparatus recited in claim 11 , wherein the multiple memory access instructions utilize different portions of the available bus width.

16. The apparatus recited in claim 11 , wherein the processor is further configured to determine that the multiple memory access instructions target the adjacent memory in response to the multiple memory access instructions including a first memory access instruction that alters a value stored in the common base register and a second memory access that accesses memory at a location adjacent to the altered value stored in the common base register.

17. The apparatus recited in claim 11 , wherein the processor is further configured to determine that the multiple memory access instructions appear non-consecutively in the processor pipeline and to replace the multiple memory access instructions with the one equivalent memory access instruction if no intervening store instructions appear between the non-consecutive memory access instructions.

18. The apparatus recited in claim 11 , wherein the processor is further configured to determine that the multiple memory access instructions appear non-consecutively in the processor pipeline and to replace the multiple memory access instructions with the one equivalent memory access instruction if one or more intervening store instructions appearing between the non-consecutive memory access instructions use the common base register referenced in the multiple memory access instructions and there are no overlapping bytes between the non-consecutive memory access instructions and the one or more intervening store instructions.

19. The apparatus recited in claim 11 , wherein the multiple memory access instructions comprise multiple dynamic instances of the same memory access instruction.

20. The apparatus recited in claim 11 , wherein the multiple memory access instructions comprise multiple load instructions or multiple store instructions.

21. An apparatus, comprising:

means for identifying, in a processor pipeline, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width, wherein the multiple memory access instructions are one of an assembly code instruction or a compiled code instruction, wherein the at least one pattern of multiple memory access instructions is identified based on an attribute of each of the multiple memory access instructions and the attributes of the multiple memory access instructions are stored in a storage instruction table;

means for determining that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line based on the attributes of the multiple memory access instructions stored in the storage instruction table;

means for determining whether a one equivalent memory access instruction to replace the multiple memory access instructions creates a memory hazard where the one equivalent memory access instruction utilizes more of the available bus width than either of the replaced memory access instructions;

means for replacing, within the processor pipeline, the multiple memory access instructions with the one equivalent memory access instruction when the one equivalent memory access instruction does not create the memory hazard; and

means for updating the storage instruction table to track the multiple memory access instructions replaced with the one equivalent memory access instruction.

22. The apparatus recited in claim 21 , wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to the multiple memory access instructions appearing consecutively in the processor pipeline and targeting the adjacent memory at contiguous offsets.

23. The apparatus recited in claim 22 , wherein the multiple memory access instructions target the adjacent memory at contiguous positive offsets.

24. The apparatus recited in claim 22 , wherein the multiple memory access instructions target the adjacent memory at contiguous negative offsets.

25. The apparatus recited in claim 21 , wherein the multiple memory access instructions utilize different portions of the available bus width.

26. The apparatus recited in claim 21 , further comprising means for determining that the multiple memory access instructions target the adjacent memory in response to the multiple memory access instructions including a first memory access instruction that alters a value stored in the common base register and a second memory access that accesses memory at a location adjacent to the altered value stored in the common base register.

27. The apparatus recited in claim 21 , further comprising means for determining that the multiple memory access instructions appear non-consecutively in the processor pipeline, wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction if no intervening store instructions appear between the non-consecutive memory access instructions.

28. The apparatus recited in claim 21 , further comprising means for determining that the multiple memory access instructions appear non-consecutively in the processor pipeline, wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction if one or more intervening store instructions appearing between the non-consecutive memory access instructions use the common base register referenced in the multiple memory access instructions and there are no overlapping bytes between the non-consecutive memory access instructions and the one or more intervening store instructions.

29. The apparatus recited in claim 21 , wherein the multiple memory access instructions comprise multiple dynamic instances of the same memory access instruction.

30. The apparatus recited in claim 21 , wherein the multiple memory access instructions comprise multiple load instructions or multiple store instructions.

31. A non-transitory computer-readable medium having computer-executable instructions recorded thereon, the computer-executable instructions configured to cause a processor to:

identify, in a pipeline associated with the processor, at least one pattern of multiple memory access instructions that reference a common base register and do not fully utilize an available bus width, wherein the multiple memory access instructions are one of an assembly code instruction or a compiled code instruction, wherein the at least one pattern of multiple memory access instructions is identified based on an attribute of each of the multiple memory access instructions and the attributes of the multiple memory access instructions are stored in a storage instruction table;

determine that the multiple memory access instructions target adjacent memory or non-contiguous memory that can fit on a single cache line based on the attributes of the multiple memory access instructions stored in the storage instruction table;

determine whether a one equivalent memory access instruction to replace the multiple memory access instructions creates a memory hazard where the one equivalent memory access instruction utilizes more of the available bus width than either of the replaced memory access instructions;

replace, within the pipeline associated with the processor, the multiple memory access instructions with the one equivalent memory access instruction when the one equivalent memory access instruction does not create the memory hazard; and

update the storage instruction table to track the multiple memory access instructions replaced with the one equivalent memory access instruction.

32. The non-transitory computer-readable medium recited in claim 31 , wherein the multiple memory access instructions are replaced with the one equivalent memory access instruction in response to the multiple memory access instructions appearing consecutively in the pipeline and targeting the adjacent memory at contiguous offsets.

33. The non-transitory computer-readable medium recited in claim 32 , wherein the multiple memory access instructions target the adjacent memory at contiguous positive offsets.

34. The non-transitory computer-readable medium recited in claim 32 , wherein the multiple memory access instructions target the adjacent memory at contiguous negative offsets.

35. The non-transitory computer-readable medium recited in claim 31 , wherein the multiple memory access instructions utilize different portions of the available bus width.

36. The non-transitory computer-readable medium recited in claim 31 , wherein the computer-executable instructions are further configured to cause the processor to determine that the multiple memory access instructions target the adjacent memory in response to the multiple memory access instructions including a first memory access instruction that alters a value stored in the common base register and a second memory access that accesses memory at a location adjacent to the altered value stored in the common base register.

37. The non-transitory computer-readable medium recited in claim 31 , wherein the computer-executable instructions are further configured to cause the processor to determine that the multiple memory access instructions appear non-consecutively in the processor pipeline and to replace the multiple memory access instructions with the one equivalent memory access instruction if no intervening store instructions appear between the non-consecutive memory access instructions.

38. The non-transitory computer-readable medium recited in claim 31 , wherein the computer-executable instructions are further configured to cause the processor to determine that the multiple memory access instructions appear non-consecutively in the processor pipeline and to replace the multiple memory access instructions with the one equivalent memory access instruction if one or more intervening store instructions appearing between the non-consecutive memory access instructions use the common base register referenced in the multiple memory access instructions and there are no overlapping bytes between the non-consecutive memory access instructions and the one or more intervening store instructions.

39. The non-transitory computer-readable medium recited in claim 31 , wherein the multiple memory access instructions comprise multiple dynamic instances of the same memory access instruction.

40. The non-transitory computer-readable medium recited in claim 31 , wherein the multiple memory access instructions comprise multiple load instructions or multiple store instructions.