Display device improving response speed of a gate clock signal or eliminating delay in the gate clock signal
A display device includes a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images, a data driver driving the data lines, a gate driver driving the gate lines, a clock generator outputting a gate clock signal, which drives the gate driver and swings between a gate-on voltage and a gate-off voltage, and a signal controller outputting a gate pulse signal which drives the clock generator and a data control signal which controls the data driver. The clock generator includes a voltage maintainer maintaining the gate clock signal at a reference voltage that has a fixed value between the gate-on voltage and the gate-off voltage for a predetermined time.
1. A display device, comprising:
a display panel including a plurality of pixels, which are connected to a plurality of gate lines and a plurality of data lines, and which display a plurality of consecutive frames of images;
a data driver which drives the data lines;
a gate driver which drives the gate lines;
a clock generator which outputs a gate clock signal which drives the gate driver and swings between a gate-on voltage and a gate-off voltage; and
a signal controller which outputs a gate pulse signal which drives the clock generator and a data control signal which controls the data driver,
wherein the clock generator comprises:
a charge sharer comprising first and second transistors connected in series with each other;
a first impedance control circuit connected to the first transistor;
a first switching circuit connecting the first impedance control circuit or one of the gate-on voltage and the gate-off voltage to a first output terminal of the clock generator;
a second impedance control circuit connected to the second transistor;
a second switching circuit connecting the second impedance control circuit or one of the gate-on voltage and the gate-off voltage to a second output terminal of the clock generator; and
a third switching circuit configured to provide one of the gate-on voltage and the gate-off voltage to the charge sharer in response to the gate pulse signal;
wherein the first and second impedance control circuits controls a slew rate of the gate clock signal by adjusting impedances of the first and second impedance control circuits.
2. The display device of claim 1 , wherein the charge sharer further comprises:
a charge sharing resistor connected to a node between the first and second transistors; and
a shared amplifier connected to the charge sharing resistor to drive the first and second transistors.
3. The display device of claim 2 , wherein the gate clock generator further comprises:
a fourth switching circuit which provides one of the gate-on voltage and the gate-off voltage to the first switching circuit in response to the gate pulse signal; and
a fifth switching circuit which provides one of the gate-on voltage and the gate-off voltage to the second switching circuit in response to the gate pulse signal,
wherein the charge sharer is configured to provide a voltage which swings between the gate-on voltage and the gate-off voltage to the first and second switching circuits.
4. The display device of claim 3 , wherein the first impedance control circuit controls the slew rate of the gate clock signal during a period when the gate clock signal swings from one of the gate-on voltage and the gate-off voltage to a reference voltage between the gate-on voltage and the gate-off voltage.
5. The display device of claim 3 , wherein the second impedance control circuit which controls the slew rate of the gate clock signal during a period when the gate clock signal swings from a reference voltage between the gate-on voltage or the gate-off voltage to one of the gate-on voltage and the gate-off voltage.