Passivation layer for a semiconductor device and method for manufacturing the same
A semiconductor device includes an ultra-thick metal (UTM) structure. The semiconductor device includes a passivation layer including a first passivation oxide. The first passivation oxide includes an unbias film and a first bias film, where the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film. The passivation layer includes a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film. The passivation layer includes a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.
1. A semiconductor device, comprising:
an ultra-thick metal (UTM) structure; and
a passivation layer including:
a first passivation oxide comprising an unbias film and a first bias film,
wherein the unbias film is on portions of the UTM structure and on portions of a layer on which the UTM structure is formed, and the first bias film is on the unbias film;
a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film; and
a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film.
2. The semiconductor device of claim 1 , wherein a total thickness of the first passivation oxide and the second passivation oxide in a region between adjacent portions of the UTM structure is greater than 50% of a height of a given portion of the UTM structure.
3. The semiconductor device of claim 1 , wherein a total thickness of the first passivation oxide, the second passivation oxide, and the third passivation oxide between adjacent portions of the UTM structure is greater than a height of a given portion of the UTM structure.
4. The semiconductor device of claim 1 , wherein the passivation layer has a profile angle of at least approximately 110 degrees in a region between adjacent portions of the UTM structure, where the profile angle is an angle between a portion of a surface of the passivation layer over an approximate middle of a gap between the adjacent portions of the UTM structure and a portion of the surface of the passivation layer over an edge of one of the adjacent portions of the UTM structure.
5. The semiconductor device of claim 1 , wherein a thickness of the first passivation oxide is less than or equal to approximately 80% of a thickness of the second passivation oxide in a region between adjacent portions of the UTM structure.
6. The semiconductor device of claim 1 , wherein a thickness of the third passivation oxide is less than or equal to approximately 80% of a thickness of the second passivation oxide in a region between adjacent portions of the UTM structure.
7. The semiconductor device of claim 1 , wherein a thickness of the third passivation oxide is less than or equal to a thickness of the first passivation oxide in a region between adjacent portions of the UTM structure.
8. A method, comprising:
forming an unbias film on an ultra-thick metal (UTM) structure of a semiconductor device and on portions of a layer of the semiconductor device on which the UTM structure is formed;
forming a first bias film on the unbias film;
forming a second bias film on the first bias film; and
forming a third bias film on the second bias film.
9. The method of claim 8 , wherein a height of a surface of the second bias film in a region between adjacent portions of the UTM structure is higher than a midpoint of a height of a given portion of the UTM structure.
10. The method of claim 8 , wherein a height of a surface of the third bias film in a region between adjacent portions of the UTM structure is greater than a height of a given portion of the UTM structure.
11. The method of claim 8 , wherein a surface of the third bias film has profile angle of at least approximately 110 degrees in a region between adjacent portions of the UTM structure.
12. The method of claim 8 , wherein a ratio of a total thickness of the unbias film and the first bias film in a region between adjacent portions of the UTM structure to a thickness of the second bias film in the region between the adjacent portions of the UTM structure is less than or equal to approximately 0.8.
13. The method of claim 8 , wherein a ratio of a thickness of the third bias film in a region between adjacent portions of the UTM structure to a thickness of the second bias film in the region between the adjacent portions of the UTM structure is less than or equal to approximately 0.8.
14. The method of claim 8 , wherein a ratio of a thickness of the third bias film in a region between adjacent portions of the UTM structure to a total thickness of the unbias film and the first bias film in the region between the adjacent portions of the UTM structure is less than or equal to approximately 1.0.
15. A semiconductor device, comprising:
a passivation layer comprising:
a first passivation oxide consisting of an unbias film and a first bias film,
wherein the unbias film is on a portion of an ultra-thick metal (UTM) structure and on a portion of another layer in a region adjacent to the portion of the UTM structure;
a second passivation oxide consisting of a second bias film, the second bias film being on the first bias film; and
a third passivation oxide consisting of a third bias film, the third bias film being on the second bias film,
wherein a height of an interface between the second passivation oxide and the third passivation oxide in a region over the portion of the other layer is more than 50% of a height of the portion of the UTM structure.
16. The semiconductor device of claim 15 , wherein a total thickness of the first passivation oxide, the second passivation oxide, and the third passivation oxide over the portion of the other layer is greater than a height of the portion of the UTM structure.
17. The semiconductor device of claim 15 , wherein the passivation layer has a profile angle of at least approximately 110 degrees over the portion of the other layer.
18. The semiconductor device of claim 15 , wherein a height of an interface between the first passivation oxide and the second passivation oxide over the portion of the other layer is less than 50% of the height of the portion of the UTM structure.
19. The semiconductor device of claim 15 , wherein a midpoint in a height of the portion of the UTM structure matches a midpoint of a thickness of the second passivation oxide in the region over the portion of the other layer.
20. The semiconductor device of claim 15 , wherein a thickness of the second passivation oxide in the region over the portion of the other layer is greater than a thickness of the first passivation oxide in the region over the portion of the other layer and is greater than a thickness of the third passivation oxide in the region over the portion of the other layer.