3-d dram cell with mechanical stability
Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.
1. A memory device comprising:
a first memory cell, a first active region, a first word line, a first capacitor, and a first bit line, the first memory cell extending along a first direction, a second direction, and a third direction; and
a second memory cell, a second active region, a second word line, a second capacitor, and a second bit line, the second memory extending along the first direction, the second direction, and the third direction, the second memory cell adjacent to and electrically isolated from the first memory cell along the first direction and connected to the first memory cell by at least one support extending in the second direction,
wherein the first memory cell and the second memory cell independently comprise a stack of alternating layers of a first material layer, a second material layer, a semiconductor material layer, and a sacrificial layer.
2. The memory device of claim 1 , wherein the at least one support comprises the first material layer and the second material layer.
3. The memory device of claim 1 , wherein the semiconductor material layer comprises a poly-silicon layer.
4. The memory device of claim 1 , wherein the first material layer and the second material layer independently comprise an insulating material.
5. The memory device of claim 4 , wherein the first material layer comprises a nitride layer and the second material layer comprises an oxide layer.
6. The memory device of claim 5 , wherein the first material layer comprises silicon nitride and the second material layer comprises silicon oxide.
7. A method of forming a memory device, the method comprising:
forming a memory stack, the memory stack extending along a first direction, a second direction, and a third direction and comprising a sacrificial layer, and alternating layers of a first material layer, a second material layer, and a semiconductor material layer; and
patterning the memory stack along the first direction to form at least one support extending along the second direction, the at least one support comprising the sacrificial layer, the first material layer, the second material layer, and the semiconductor material layer.
8. The method of claim 7 , further comprising removing the semiconductor material layer from the support to form an opening.
9. The method of claim 8 , further comprising depositing an insulating layer to fill the opening.
10. The method of claim 9 , wherein the insulating layer comprises silicon oxide.
11. The method of claim 7 , wherein the first material layer and the second material layer independently comprise an insulating material.
12. The method of claim 11 , wherein the first material layer comprises a nitride layer and the second material layer comprises an oxide layer.
13. The method of claim 12 , wherein the first material layer comprises silicon nitride and the second material layer comprises silicon oxide.
14. The method of claim 7 , wherein the semiconductor material layer comprises a poly-silicon layer.
15. The method of claim 9 , further comprising forming an active opening through the memory stack and recessing the first material layer through the opening.
16. The method of claim 15 , further comprising:
depositing a gate oxide layer;
forming a word line, the word line comprising one or more of a barrier layer and a word line metal;
depositing a fill material in the active opening;
forming a capacitor opening through the memory stack;
forming a capacitor in the capacitor opening;
forming a bit line opening in the fill material; and
forming a bit line in the bit line opening.
17. The method of claim 16 , wherein forming the capacitor opening comprises slit patterning the memory stack and depositing one or more of a lower electrode, a high-k dielectric layer, a top electrode, and a silicon germanium (SiGe) layer.
18. A non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, causes the processing chamber to perform the operations of:
form a memory stack, the memory stack extending along a first direction, a second direction, and a third direction and comprising a sacrificial layer, and alternating layers of a first material layer, a second material layer, and a semiconductor material layer; and
pattern the memory stack along the first direction to form at least one support extending along the second direction, the at least one support comprising the sacrificial layer, the first material layer, the second material layer, and the semiconductor material layer.
19. The non-transitory computer readable medium of claim 18 that includes further instructions that, when executed by a controller of a processing chamber, causes the processing chamber to perform the further operations of:
remove the semiconductor material layer from the support to form an opening;
deposit an insulating layer to fill the opening;
form an active opening through the memory stack;
recess the first material layer through the active opening;
deposit a gate oxide layer;
form a word line, the word line comprising one or more of a barrier layer and a word line metal;
deposit a fill material in the opening;
form a capacitor opening through the memory stack;
form a capacitor in the capacitor opening;
form a bit line opening in the fill material; and
form a bit line in the bit line opening.