Semiconductor device and method

1. A semiconductor device comprising:

a gate structure over a semiconductor substrate, the gate structure comprising:

a high-k dielectric layer, the high-k dielectric layer extending a first height above the substrate;

an n-type work function layer over the high-k dielectric layer, the n-type work function layer extending a second height, less than the first height, above the substrate;

an anti-reaction layer over the n-type work function layer, the anti-reaction layer comprising a dielectric material and extending the second height above the substrate;

a p-type work function layer over the anti-reaction layer, the p-type work function layer covering top surfaces of the anti-reaction layer and extending a third height above the substrate, the third height being greater than the second height; and

a conductive cap layer over the p-type work function layer.

2. The semiconductor device of claim 1 , wherein the p-type work function layer is T-shaped in a cross-sectional view.

3. The semiconductor device of claim 1 , wherein the anti-reaction layer comprises silicon.

4. The semiconductor device of claim 1 , wherein the conductive cap layer comprises tungsten.

5. The semiconductor device of claim 1 , wherein top surfaces of the high-k dielectric layer are level with a top surface of the p-type work function layer.

6. The semiconductor device of claim 5 , further comprising gate spacers adjacent the gate structure, wherein the conductive cap layer extends between opposite side surfaces of the gate spacers, and wherein top surfaces of the gate spacer are level with a top surface of the conductive cap layer.

7. The semiconductor device of claim 1 , further comprising gate spacers adjacent the gate structure, wherein a top surface of the p-type work function layer is level with top surfaces of the high-k dielectric layer and top surfaces of the gate spacers.

8. A semiconductor device comprising:

a first channel region in an n-type region;

a second channel region in a p-type region;

a first gate stack over the first channel region, the first gate stack comprising:

a first gate dielectric layer over the first channel region;

an n-type metal layer over and in contact with the first gate dielectric layer, the n-type metal layer comprising aluminum;

a dielectric layer over the n-type metal layer;

a first p-type metal layer over the n-type metal layer and the dielectric layer; and

a first metal cap layer over the first p-type metal layer; and

a second gate stack over the second channel region, the second gate stack comprising:

a second gate dielectric layer over the second channel region;

a second p-type metal layer over and in contact with the second gate dielectric layer; and

a second metal cap layer over the second p-type metal layer; and

wherein a combined height of the n-type metal layer, the dielectric layer, and the first p-type metal layer is equal to a height of the second p-type metal layer.

9. The semiconductor device of claim 8 , wherein the dielectric layer and the first p-type metal layer are in contact with the first gate dielectric layer.

10. The semiconductor device of claim 8 , wherein the dielectric layer comprises silicon.

11. The semiconductor device of claim 8 , wherein the first metal cap layer and the second metal cap layer comprise chlorine.

12. The semiconductor device of claim 8 , wherein a top surface of the first p-type metal layer is level with a top surface of the second p-type metal layer, and wherein a bottom surface of the second p-type metal layer is below a bottom surface of the first p-type metal layer.

13. The semiconductor device of claim 8 , further comprising:

a first gate spacer extending along a sidewall of the first gate stack; and

a second gate spacer extending along a sidewall of the second gate stack, wherein a top surface of the second gate spacer is level with a top surface of the second metal cap layer, a top surface of the first gate spacer, and a top surface of the first metal cap layer.

14. The semiconductor device of claim 8 , wherein the first p-type work function layer is T-shaped in a cross-sectional view.

15. A method comprising:

forming a gate stack over a semiconductor substrate, wherein forming the gate stack comprises:

depositing an n-type work function layer over a portion of the semiconductor substrate;

depositing a dielectric layer over the n-type work function layer;

forming a first mask layer over the dielectric layer;

etching back an upper portion of the n-type work function layer and an upper portion of the dielectric layer while leaving remaining a lower portion of the n-type work function layer and a lower portion of the dielectric layer, the respective lower portions being directly below the respective upper portions before the etching back step;

depositing a p-type work function layer over the lower portion of the n-type work function layer and the lower portion of the dielectric layer; and

selectively depositing a metal cap layer over the p-type work function layer.

16. The method of claim 15 , wherein the metal cap layer is deposited by atomic layer deposition using tungsten chloride as a precursor.

17. The method of claim 15 , wherein the n-type work function layer and the dielectric layer are etched back using the first mask layer as a mask, and wherein the first mask layer is removed before depositing the p-type work function layer.

18. The method of claim 15 , further comprising etching back the dielectric layer to expose the n-type work function layer, wherein the p-type work function layer is deposited in contact with the n-type work function layer and the dielectric layer.

19. The method of claim 15 , further comprising:

forming a gate spacer adjacent a sacrificial gate stack;

removing the sacrificial gate stack to form a first opening, wherein the gate stack is formed in the first opening;

planarizing the gate spacer and the p-type work function layer; and

etching back the p-type work function layer after planarizing the gate spacer and the p-type work function layer.

20. The method of claim 19 , further comprising etching back the gate spacer, wherein the metal cap layer is deposited between opposite side surfaces of the gate spacer.