IP Library › Granted Patent US 11,594,638
Granted Patent B2
US 11,594,638 · App. 17/146,581 · Granted Feb 28, 2023

Epitaxial structures for semiconductor devices

Inventor: Shahaji B. More (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/78618H01L21/02532H01L21/02603H01L21/26513H01L21/28518H01L29/0673H01L29/42392H01L29/45H01L29/66553H01L29/66742H01L29/78696
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Quick Facts
Patent No.
US 11,594,638
App. No.
17/146,581
Granted
Feb 28, 2023
Kind
B2
Abstract

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes nanostructures on a substrate and a source/drain region in contact with the nanostructures. The source/drain region includes epitaxial end caps, where each epitaxial end cap is formed at an end portion of a nanostructure of the nanostructures. The source/drain region also includes an epitaxial body in contact with the epitaxial end caps and an epitaxial top cap formed on the epitaxial body. The semiconductor device further includes gate structure formed on the nanostructures.

Claims (44)

1. A semiconductor device, comprising:

a plurality of nanostructures on a substrate;

a source/drain region in contact with the plurality of nanostructures, comprising:

a plurality of epitaxial end caps, wherein each epitaxial end cap is formed at an end portion of a nanostructure of the plurality of nanostructures;

an epitaxial body in contact with the plurality of epitaxial end caps; and

an epitaxial top cap formed on the epitaxial body;

a gate structure formed on the plurality of nanostructures; and

a dielectric layer disposed on one of the nanostructures of the plurality of nanostructures and in contact with one of the epitaxial end caps of the plurality of epitaxial end caps.

2. The semiconductor device of claim 1 , wherein each epitaxial end cap of the plurality of epitaxial end caps comprises a crescent cross-sectional shape.

3. The semiconductor device of claim 1 , wherein each nanostructure of the plurality of nanostructures comprises a non-planar outer surface and each epitaxial end cap of the plurality of end caps comprises an inner surface contouring to the non-planar outer surface.

4. The semiconductor device of claim 1 , further comprising a plurality of inner spacers, wherein an inner spacer of the plurality of inner spacers is formed between adjacent nanostructures of the plurality of nanostructures.

5. The semiconductor device of claim 4 , wherein an epitaxial end cap of the plurality of epitaxial end caps is in contact with the inner spacer.

6. The semiconductor device of claim 1 , further comprising an epitaxial base formed in a groove of the substrate, wherein the epitaxial base and the plurality of epitaxial end caps are formed using a same material.

7. The semiconductor device of claim 6 , wherein the epitaxial body comprises a first atomic concentration of germanium and the epitaxial base comprises a second atomic concentration of germanium that is lower than the first atomic concentration of germanium.

8. The semiconductor device of claim 1 , wherein the epitaxial body comprises a first atomic concentration of germanium and the plurality of epitaxial end caps comprises a second atomic concentration of germanium that is lower than the first atomic concentration of germanium.

9. The semiconductor device of claim 1 , wherein the epitaxial body comprises a first atomic concentration of germanium and the epitaxial top cap comprises a second atomic concentration of germanium that is greater than the first atomic concentration of germanium.

10. The semiconductor device of claim 1 , wherein the epitaxial body comprises a non-uniform atomic concentration of germanium that decreases from a top surface to a bottom surface of the epitaxial body.

11. A semiconductor device, comprising:

a plurality of nanostructures, wherein a nanostructure of the plurality of nanostructures comprises a non-planar outer surface;

a gate dielectric layer wrapping around each nanostructure of the plurality of nanostructures;

a gate electrode disposed on the gate dielectric layer and on the plurality of nanostructures; and

a source/drain region in contact with the plurality of nanostructures, comprising:

a plurality of epitaxial end caps, wherein an epitaxial end cap is formed at an end portion of the nanostructure and comprises a first dopant concentration, and wherein one of the epitaxial end caps of the plurality of end caps comprises an inner surface contouring to the non-planar outer surface of the nanostructure; and

an epitaxial body in contact with the epitaxial end cap and comprising a second dopant concentration greater than the first dopant concentration.

12. The semiconductor device of claim 11 , further comprising an epitaxial top cap formed on the epitaxial body, wherein the epitaxial top cap comprises a third dopant concentration greater than the second dopant concentration.

13. The semiconductor device of claim 11 , wherein the epitaxial end cap comprises a crescent cross-sectional shape.

14. The semiconductor device of claim 11 , further comprising a plurality of spacers, wherein a spacer of the plurality of spacers is in contact with the epitaxial end cap and with the nanostructure of the plurality of nanostructures.

15. The semiconductor device of claim 14 , wherein the spacer is in contact with the epitaxial body.

16. A method, comprising:

forming a plurality of nanostructures on a substrate;

forming a plurality of spacers, wherein each spacer is between a pair of nanostructures of the plurality of nanostructures;

etching the substrate to form a recess;

depositing a first epitaxial layer on sidewalls of the plurality of nanostructures, sidewalls of the plurality of spacers, and in the recess;

etching the first epitaxial layer to form a plurality of epitaxial end caps and an epitaxial base in the recess, wherein each epitaxial end cap is formed on a sidewall ofa nanostructure of the plurality of nanostructures and the epitaxial base is in contact with a spacer of the plurality of spacers;

depositing a second epitaxial layer on the plurality of end caps and the epitaxial base;

etching the second epitaxial layer; and

depositing a third epitaxial layer on the etched second epitaxial layer.

17. The method of claim 16 , wherein etching the first epitaxial layer comprises forming a crescent cross-sectional shape for each epitaxial end cap.

18. The method of claim 16 , wherein depositing the second epitaxial layer comprises implanting, into the second epitaxial layer, a dopant with a dopant concentration greater than a dopant concentration of the first epitaxial layer.

19. The method of claim 16 , further comprising:

etching the third epitaxial layer;

forming a silicide layer on the etched third epitaxial layer; and

forming a source/drain contact on the silicide layer.

20. The method of claim 16 , further comprising implanting, into the third epitaxial layer, a dopant with a dopant concentration greater than a dopant concentration of the second epitaxial layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2021
From: MORE, SHAHAJI B.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054894/0430 →
Continuity (2)
Provisional Application 63065686 · Aug 14, 2020
Related Publication 20220052203A1 · Feb 17, 2022