IP Library › Granted Patent US 11,595,060
Granted Patent B2
US 11,595,060 · App. 17/377,643 · Granted Feb 28, 2023

Method and apparatus for decoding low-density parity-check code

Inventor: Nam Il Kim (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H03M13/1117
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Quick Facts
Patent No.
US 11,595,060
App. No.
17/377,643
Granted
Feb 28, 2023
Kind
B2
Abstract

A method for decoding a low-density parity-check (LDPC) code, performed by a communication apparatus, includes: updating a variable node; determining n minimum values based on a min-sum algorithm (MSA); determining n indices based on the n minimum values; updating a check node using the n indices; calculating a log-likelihood ratio (LLR) value when the update of the check node is completed; and determining an information bit based on the LLR value.

Claims (28)

1. A method for decoding a low-density parity-check (LDPC) code, performed by a first communication apparatus, the method comprising:

receiving a signal including data from a second communication apparatus;

updating a variable node for decoding the signal;

determining a first minimum value (v1), a second minimum value (v2), and a third minimum value (v3) based on a min-sum algorithm (MSA);

calculating f(v2,v3) based on f(v2,v3)=(v2*v3)/(v2+v3) when the v1 is the smallest value among the v1, the v2, and the v3, calculating f(v1,v3) based on f(v1,v3)=(v1*v3)/(v1+v3) when the v2 is the smallest value among the v1, the v2, and the v3, or calculating f(v1,v2) based on f(v1,v2)=(v1*v2)/(v1+v2) when the v3 is the smallest value among the v1, the v2, and the v3;

updating a check node using the f(v2,v3), the f(v1,v3), or the f(v1,v2);

calculating a log-likelihood ratio (LLR) value when the update of the check node is completed;

determining an information bit based on the LLR value; and

restoring the data included in the signal based on the information bit.

2. The method according to claim 1 , wherein the check node is updated based on the MSA in which a normalization coefficient is reflected.

3. The method according to claim 1 , wherein the check node is updated based on the MSA in which an offset is reflected.

4. The method according to claim 1 , further comprising initializing one or more parameters used for decoding the LDPC code,

wherein after the initialization of the one or more parameters is completed, the update operation of the variable node is performed.

5. The method according to claim 1 , wherein the variable node and the check node belong to a Tanner graph, and the Tanner graph is generated based on an H matrix used for encoding the LDPC code.

6. The method according to claim 1 , wherein when a cyclic redundancy check (CRC) or syndrome check for the information bit succeeds, the decoding of the LDPC code is terminated, and when the CRC or syndrome check for the information bit fails, the decoding is iteratively performed.

7. A first communication apparatus for decoding a low-density parity-check (LDPC) code, the first communication apparatus comprising a processor, a memory electronically communicating with the processor, and instructions stored in the memory, wherein when executed by the processor, the instructions cause the first communication apparatus to:

receive a signal including data from a second communication apparatus;

update a variable node for decoding the signal;

determine a first minimum value (v1), a second minimum value (v2), and a third minimum value (v3) based on a min-sum algorithm (MSA);

calculate f(v2,v3) based on f(v2,v3)=(v2*v3)/(v2+v3) when the v1 is the smallest value among the v1, the v2, and the v3, calculate f(v1,v3) based on f(v1,v3)=(v1*v3)/(v1+v3) when the v2 is the smallest value among the v1, the v2, and the v3, or calculate f(v1,v2) based on f(v1,v2)=(v1*v2)/(v1+v2) when the v3 is the smallest value among the v1, the v2, and the v3;

update a check node using the f(v2,v3), the f(v1,v3), or the f(v1,v2);

calculate a log-likelihood ratio (LLR) value when the update of the check node is completed;

determine an information bit based on the LLR value; and

restore the data included in the signal based on the information bit.

8. The first communication apparatus according to claim 7 , wherein the check node is updated based on the MSA in which a normalization coefficient is reflected.

9. The first communication apparatus according to claim 7 , wherein the check node is updated based on the MSA in which an offset is reflected.

10. The first communication apparatus according to claim 7 , wherein the variable node and the check node belong to a Tanner graph, and the Tanner graph is generated based on an H matrix used for encoding the LDPC code.

11. The first communication apparatus according to claim 7 , wherein when a cyclic redundancy check (CRC) or syndrome check for the information bit succeeds, the decoding of the LDPC code is terminated, and when the CRC or syndrome check for the information bit fails, the decoding is iteratively performed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2021
From: KIM, NAM IL
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 056879/0092 →
Priority Claims (1)
KR 10-2020-0094725 · Jul 29, 2020 · national
Continuity (1)
Related Publication 20220038114A1 · Feb 3, 2022
Cited By (4)
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