Vertical memory with simplified integration
A vertical memory device is provided including a first structure on a substrate. The first structure includes gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers. A second structure is connected to the first structure. The second structure includes pad patterns electrically connected to the gate patterns of a respective one of the layers. A channel structure passes through the gate patterns. A first contact plug passes through the second structure and electrically connects with a pad pattern of one of the layers. The first contact plug is electrically insulated from gate patterns of other layers. At least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug.
1. A vertical memory device, comprising:
a first structure on a substrate, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate to form a plurality of layers;
a second structure connected to the first structure, the second structure including pad patterns electrically connected to the gate patterns of a respective one of the layers;
a channel structure passing through the gate patterns; and
a first contact plug passing through the second structure and electrically connected with a pad pattern of one of the layers, wherein the first contact plug is electrically insulated from gate patterns of other layers through which the first contact plug passes,
wherein at least one bent portion is included at each of a sidewall of the channel structure and a sidewall of the first contact plug,
wherein the bent portion of the channel structure and the bent portion of the first contact plug are coplanar with each other.
2. The vertical memory device of claim 1 , wherein an upper surface of the channel structure and an upper surface of the first contact plug are coplanar with each other.
3. The vertical memory device of claim 1 , wherein a lower surface of the channel structure is higher than a lower surface of the first contact plug.
4. The vertical memory device of claim 1 , further comprising:
a circuit pattern formed on the substrate;
a lower pad electrically connected to the circuit pattern; and
a base pattern and a base insulation layer on the lower pad,
wherein the first structure and the second structure are formed on the base pattern or the base insulation layer.
5. The vertical memory device of claim 4 , wherein a lower surface of the channel structure contacts the base pattern, and a lower surface of the first contact plug contacts the lower pad.
6. The vertical memory device of claim 1 , further comprising:
a third structure spaced apart from the second structure, and the third structure including an insulation material; and
a second contact plug passing through the third structure, and the second contact plug including a bent portion at a sidewall thereof.
7. The vertical memory device of claim 6 , further comprising:
a first upper wiring on the channel structure, the first upper wiring electrically connected to the channel structure; and
a second upper wiring on the second contact plug, the second upper wiring electrically connected to the second contact plug.
8. The vertical memory device of claim 1 , further comprising an insulating interlayer covering the first structure and the second structure, and
wherein an upper surface of the insulating interlayer is coplanar with upper surfaces of each of the channel structure and the first contact plug.
9. The vertical memory device of claim 8 , wherein the bent portion of the channel structure is positioned between the first structure and the insulating interlayer, and the bent portion of the first contact plug is positioned between the second structure and the interlayer insulating layer.
10. A vertical memory device, comprising:
a circuit pattern on a substrate;
a base pattern and a base insulation layer on the circuit pattern;
a first structure on the base pattern, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the gate patterns extending in a first direction parallel to the upper surface of the substrate;
a second structure connected to the first structure, the second structure including pad patterns in separate layers, wherein the pad patterns are electrically connected to the gate patterns of a same layer;
a channel structure passing through the gate patterns, and the channel structure extending in the vertical direction;
a first contact plug passing through the second structure and electrically connected with a pad pattern of one of the layers, and the first contact plug extending in the vertical direction; and
at least one bent portion is included at a sidewall of the channel structure and a sidewall of the first contact plug,
wherein the bent portion of the channel structure and the bent portion of the first contact plug are coplanar with each other, and
wherein an upper surface of the channel structure and an upper surface of the first contact plug are coplanar with each other.
11. The vertical memory device of claim 10 , further comprising an insulating interlayer covering the first structure and the second structure, and
wherein an upper surface of the insulating interlayer is coplanar with upper surfaces of at least one of the channel structure and the first contact plug.
12. The vertical memory device of claim 10 , wherein a lower surface of the channel structure contacts an upper surface of the base pattern, and the first contact plug passes through the base insulation layer, and wherein a lower surface of the first contact plug is disposed lower than the lower surface of the channel structure.
13. The vertical memory device of claim 10 , further comprising a lower pad electrically connected to the circuit pattern, and
wherein a sidewall of the first contact plug contacts a portion of the pad pattern, and a lower surface of the first contact plug contacts the lower pad.
14. A vertical memory device, comprising:
a first structure on a substrate, the first structure including gate patterns spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, and the gate patterns extending in a first direction parallel to the upper surface of the substrate;
a second structure connected to the first structure, the second structure including pad patterns spaced apart in separate layers and electrically connected to gate patterns of a same layer;
a channel structure passing through the gate patterns, and the channel structure extending in the vertical direction;
a first contact plug passing through the second structure and electrically connected with a pad pattern of one of the layers, and the first contact plug extending in the vertical direction, and the first contact plug passing through the second structure, wherein the first contact plug is electrically insulated from gate patterns of other layers through which the first contact plug passes;
a third structure spaced apart from the second structure; and
a second contact plug passing through the third structure, and the second contact plug extending in the vertical direction,
wherein an upper surface of the channel structure and upper surfaces of the first contact plug and the second contact plug are coplanar with each other,
wherein at least one of a sidewall of the channel structure and sidewalls of the first contact plug and the second contact plug includes at least one bent portion, and
wherein the bent portion of the channel structure and the bent portions of the first contact plug and the second contact plug are coplanar with each other.
15. The vertical memory device of claim 14 , further comprising a circuit pattern formed on the substrate, the circuit pattern disposed under the first structure and the second structure;
wherein each of the first contact plug and the second contact plug are electrically connected to the circuit pattern.