Integrated circuit device including gate line

1. An integrated circuit device comprising:

an active area extending in a first direction on a substrate; and

a gate line extending in a second direction intersecting with the first direction to intersect with the active area;

a gate dielectric layer conformally on all vertical surfaces of the gate line;

a gate spacer conformally on vertical surfaces of the gate dielectric layer which extend in the second direction; and

a gate isolation layer including a face contacting the gate dielectric layer and the gate spacer, a width of the face of the gate isolation layer is equal to a width between outer faces of the gate spacer, the outer faces being opposite one another,

wherein

the gate line comprises a first sidewall and a second sidewall opposite to each other,

the first sidewall has a convex shape, and

the second sidewall has a concave shape.

2. The integrated circuit device of claim 1 , wherein the first sidewall and the second sidewall have different curvatures.

3. The integrated circuit device of claim 1 , wherein a curvature of the first sidewall is greater than a curvature of the second sidewall.

4. The integrated circuit device of claim 1 , wherein the gate dielectric layer is between the second sidewall of the gate line and the gate isolation layer.

5. An integrated circuit device comprising:

a plurality of first active areas extending in a first direction on a substrate;

a plurality of second active areas extending in the first direction on the substrate;

a first gate line extending in a second direction intersecting with the first direction to intersect with the plurality of first active areas, the first gate line having a first width;

a second gate line extending in the second direction to intersect with the plurality of second active areas, the second gate line having a second width which is narrower than the first width;

a third gate line extending in the second direction apart from the second gate line in the second direction, the third gate line having the second width;

a first gate dielectric layer conformally on all vertical surfaces of the first gate line;

a first gate spacer conformally on vertical surfaces of the first gate dielectric layer which extend in the second direction; and

a first gate isolation layer between the second gate line and the third gate line, the first gate isolation layer including a face contacting the first gate dielectric layer and the first gate spacer, a width of the face of the gate isolation layer is equal to a width between outer faces of the first gate spacer, the outer faces being opposite one another,

wherein

the first gate line comprises a curved surface and comprises a first sidewall and a second sidewall having different curvatures, and

the first gate isolation layer contacts the second gate line and the third gate line.

6. The integrated circuit device of claim 5 , wherein the first sidewall has a convex shape.

7. The integrated circuit device of claim 5 , wherein the second sidewall has a concave shape.

8. The integrated circuit device of claim 5 , further comprising:

a fourth gate line apart from the third gate line in the second direction, the fourth gate line having the second width; and

a second gate isolation layer between the third gate line and the fourth gate line,

wherein

the third gate line is between the second gate line and the fourth gate line in the second direction, and

the second gate isolation layer is apart from the third gate line and the fourth gate line.

9. The integrated circuit device of claim 8 , further comprising:

a fifth gate line apart from the first gate line in the second direction, the fifth gate line having the first width; and

a third gate isolation layer between the first gate line and the fifth gate line,

wherein the third gate isolation layer is apart from the first gate line and the fifth gate line.

10. The integrated circuit device of claim 8 , further comprising a fifth gate line apart from the first gate line in the second direction, the fifth gate line having the first width,

wherein the fifth gate line comprises a convex sidewall facing the first sidewall.

11. An integrated circuit device comprising:

a substrate including a cell area, where a static random access memory (SRAM) cell is located, and a peri area where a peripheral circuit configured to operate the SRAM cell is located;

a first upper gate line extending in one direction in the cell area;

a first upper gate dielectric layer conformally on all vertical surfaces of the first upper gate line;

a first upper gate spacer conformally on vertical surfaces of the first upper gate dielectric layer;

a first lower gate line extending in the one direction in the cell area apart from the first upper gate line in the one direction;

a first gate isolation layer between the first upper gate line and the first lower gate line, the first gate isolation layer including a face contacting the first upper gate dielectric layer and the upper first gate spacer, a width of the face of the first gate isolation layer is equal to a width between outer faces of the first upper gate spacer, the outer faces being opposite one another;

a second upper gate line extending in one direction in the peri area;

a second lower gate line extending in the one direction in the peri area apart from the second upper gate line in the one direction; and

a second gate isolation layer between the second upper gate line and the second lower gate line,

wherein

the first gate isolation layer contacts the first upper gate line and the first lower gate line,

the second gate isolation layer is apart from the second upper gate line and the second lower gate line, and

each of the second upper gate line and the second lower gate line comprises a concave sidewall.

12. The integrated circuit device of claim 11 , wherein at least one of the second upper gate line and the second lower gate line further comprises a convex sidewall.

13. The integrated circuit device of claim 11 , wherein a width of each of the first upper gate line and the first lower gate line is less than a width of each of the second upper gate line and the second lower gate line.

14. The integrated circuit device of claim 13 , further comprising:

a third upper gate line extending in the one direction in the peri area;

a third lower gate line extending in the one direction in the peri area apart from the third upper gate line in the one direction; and

a third gate isolation layer between the third upper gate line and the third lower gate line,

wherein the third gate isolation layer contacts the third upper gate line and the third lower gate line.

15. The integrated circuit device of claim 14 , wherein a width of each of the third upper gate line and the third lower gate line is less than a width of each of the second upper gate line and the second lower gate line.

16. The integrated circuit device of claim 15 , further comprising:

a fourth upper gate line extending in the one direction in the peri area;

a fourth lower gate line extending in the one direction in the peri area apart from the fourth upper gate line in the one direction; and

a fourth gate isolation layer between the fourth upper gate line and the fourth lower gate line,

wherein the fourth gate isolation layer is apart from the fourth upper gate line and the fourth lower gate line.

17. The integrated circuit device of claim 16 , wherein a width of each of the fourth upper gate line and the fourth lower gate line is less than a width of each of the second upper gate line and the second lower gate line.

18. The integrated circuit device of claim 13 , further comprising:

a third upper gate line extending in the one direction in the peri area;

a third lower gate line extending in the one direction in the peri area apart from the third upper gate line in the one direction; and

a third gate isolation layer between the third upper gate line and the third lower gate line,

wherein the third gate isolation layer is apart from the third upper gate line and the third lower gate line.

19. The integrated circuit device of claim 18 , wherein a width of each of the third upper gate line and the third lower gate line is less than a width of each of the second upper gate line and the second lower gate line.