Multiple power management integrated circuits and apparatus having dual pin interface

1. A method of signaling between multiple power management integrated circuits (PMICs), the method comprising:

coupling a main PMIC and at least one sub-PMIC to each other through a first bidirectional line;

coupling the main PMIC to the at least one sub-PMIC to each other through a second unidirectional line;

asserting an operation associated with a power sequence of the main PMIC and the at least one sub-PMIC based on a power status signal on the first bidirectional line from the main PMIC and the at least one sub-PMIC; and

asserting an operation of controlling a power sequence of the at least one sub-PMIC by using a power sequence control signal on the second unidirectional line from the main PMIC to the at least one sub-PMIC.

2. The method of claim 1 , further comprising:

triggering a power on reset signal in the main PMIC in response to a voltage level of external power provided to the main PMIC being maintained at a desired level;

generating, by the main PMIC and the at least one sub-PMIC, the power status signal as a pulse signal with a ramping leading edge and a trailing edge as an operation result in response to the power on reset signal; and

confirming, by the main PMIC, a power ready state of the multiple PMICs based on the power status signal.

3. The method of claim 1 , further comprising:

triggering the main PMIC to power-on;

generating, by the main PMIC and the at least one sub-PMIC, the power status signal as a pulse signal with a ramping leading edge and a trailing edge and then transitioning from a logic low level to a logic high level as an operation result in response to the power-on trigger; and

confirming, by the main PMIC, a ready state of a plurality of reference voltage generators of the at least one sub-PMIC based on the power status signal.

4. The method of claim 1 , further comprising:

triggering the main PMIC to power-off;

performing, by the main PMIC, a power-off sequence of the main PMIC in response to the power-off trigger, the power-off sequence including,

generating the power status signal to be a logic low level,

generating the power sequence control signal as a preamble signal and a signal toggled at desired times during a time-out time period of a logic low level duration of the power status signal; and

performing, by the at least one sub-PMIC, clock synchronization of the at least one sub-PMIC in response to the power sequence control signal, the clock synchronization including confirming an expiration of the time-out time period of the power status signal, and

performing a power-off sequence of the at least one sub-PMIC.

5. The method of claim 1 , further comprising:

triggering the at least one sub-PMIC to power-off;

generating the power status signal as a pulse signal with a trailing edge and a ramping leading edge for a time less than a time-out time period as an operation result by the main PMIC and the at least one sub-PMIC in response to the power-off trigger;

performing, by the main PMIC, a power-off sequence of the main PMIC, the performing the power-off sequence of the main PMIC including,

generating the power status signal to be a logic low level, which has a pulse signal with a trailing edge and a ramping leading edge for a time less than the time-out time period, and

generating the power sequence control signal as a preamble signal and a signal toggled at desired times during the time-out time period of a logic low level duration of the power status signal; and

performing, by the at least one sub-PMIC, clock synchronization of the at least one sub-PMIC in response to the power sequence control signal, the clock synchronization including,

confirming expiration of the time-out time period of the power status signal, and

performing a power-off sequence of the at least one sub-PMIC.

6. The method of claim 1 , further comprising:

observing a shut-down event in the at least one sub-PMIC;

turning off, by the at least one sub-PMIC, the at least one sub-PMIC in response to the shut-down event, the turning off the at least one sub-PMIC including generating the power status signal to be a logic low level; and

confirming, by the main PMIC, expiration of a time-out time period of a low logic level duration of the power status signal, the confirming including turning off the main PMIC.

7. The method of claim 1 , further comprising:

observing a shut-down event in the main PMIC;

turning off, by the main PMIC, the main PMIC in response to the shut-down event, the turning off the main PMIC including generating the power status signal to be a logic low level; and

confirming, by the at least one sub-PMIC, expiration of a time-out time period of a low logic level duration of the power status signal, the confirming including turning off the at least one sub-PMIC.

8. The method of claim 1 , wherein the power sequence control signal is signaled based on a bi-phase Manchester code scheme.

9. The method of claim 1 , wherein the power sequence control signal includes a plurality of preamble bits, a start bit, a plurality of chip identification (ID) bits, a parity bit and a stop bit, and causes an ID check to be performed by the main PMIC of the at least one sub-PMIC.

10. The method of claim 1 , wherein the power sequence control signal includes a plurality of preamble bits, a start bit, a plurality of power-on sequence command bits, a parity bit, and a stop bit, and causes start of a power-on sequence by the main PMIC.

11. The method of claim 1 , further comprising:

generating, by the main PMIC, the power sequence control signal by generating a frequency shift time point using frequency shift keying, the frequency shift time point indicating a trigger point of a power-on or power-off sequence of the at least one sub-PMIC.