Memory management method, electronic device and storage medium

1. A memory management method, comprising:

allocating a first memory address to video frame data based on a memory multiplexing queue, wherein the memory multiplexing queue records a memory address of video frame data that has been rendered;

storing the video frame data in a memory space indicated by the first memory address; and

adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data,

wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

acquiring a second memory address from the memory multiplexing queue according to a data volume of the video frame data when the memory multiplexing queue comprises a memory address, wherein a memory space indicated by the second memory address is not less than the data volume of the video frame data; and

removing the second memory address from the memory multiplexing queue when the second memory address is acquired from the memory multiplexing queue, and taking the second memory address as the first memory address.

2. The method according to claim 1 , wherein after the acquiring a second memory address from the memory multiplexing queue according to a data volume of the video frame data, the method further comprises:

acquiring a third memory address from memory addresses other than the memory multiplexing queue when the second memory address is not acquired from the memory multiplexing queue, wherein a memory space indicated by the third memory address is not less than the data volume of the video frame data; and

taking the third memory address as the first memory address.

3. The method according to claim 1 , wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

acquiring a fourth memory address from memory addresses other than the memory multiplexing queue when the memory multiplexing queue does not comprise any memory address; and

taking the fourth memory address as the first memory address.

4. The method according to claim 1 , wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

acquiring a resolution of a video stream upon receiving the video stream, and allocating, according to a data volume of video frame data indicated by the resolution, a first memory address to video frame data based on a memory multiplexing queue.

5. The method according to claim 1 , further comprising:

launching a child thread by a specified interface of a multimedia browsing application; and

decoding the video frame data by the child thread.

6. The method according to claim 1 , further comprising:

rendering the video frame data by a main thread of a multimedia browsing application;

wherein correspondingly, the adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data comprises:

passing the first memory address to a child thread of the multimedia browsing application by the main thread, and adding the first memory address to the memory multiplexing queue by the child thread.

7. The method according to claim 1 , wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

during a process of decoding the received video stream, allocating, when the video frame data is acquired, a first memory address to video frame data based on a memory multiplexing queue.

8. The method according to claim 1 , further comprising:

rendering the video frame data by a main thread of a multimedia browsing application;

wherein correspondingly, the adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data comprises:

adding the first memory address to the memory multiplexing queue by the main thread.

9. An electronic device, comprising: a processor and a memory, wherein the memory is configured to store a computer program that when executed by the processor causes the processor to perform the following operations:

allocating a first memory address to video frame data based on a memory multiplexing queue, wherein the memory multiplexing queue records a memory address of video frame data that has been rendered;

storing the video frame data in a memory space indicated by the first memory address; and

adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data,

wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

acquiring a second memory address from the memory multiplexing queue according to a data volume of the video frame data when the memory multiplexing queue comprises a memory address, wherein a memory space indicated by the second memory address is not less than the data volume of the video frame data; and

removing the second memory address from the memory multiplexing queue when the second memory address is acquired from the memory multiplexing queue, and taking the second memory address as the first memory address.

10. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

acquiring a third memory address from memory addresses other than the memory multiplexing queue when the second memory address is not acquired from the memory multiplexing queue, wherein a memory space indicated by the third memory address is not less than the data volume of the video frame data; and

taking the third memory address as the first memory address.

11. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

acquiring a fourth memory address from memory addresses other than the memory multiplexing queue when the memory multiplexing queue does not comprise any memory address; and

taking the fourth memory address as the first memory address.

12. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

acquiring a resolution of a video stream upon receiving the video stream, and performing the step of allocating a first memory address to video frame data based on a memory multiplexing queue according to a data volume of video frame data indicated by the resolution.

13. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

performing the step of allocating a first memory address to video frame data based on a memory multiplexing queue when the video frame data is acquired during a process of decoding the received video stream.

14. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

launching a child thread by a specified interface of a multimedia browsing application; and

decoding the video frame data by the child thread.

15. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

rendering the video frame data by a main thread of a multimedia browsing application; and

passing the first memory address to a child thread of the multimedia browsing application by the main thread, and adding the first memory address to the memory multiplexing queue by the child thread.

16. The electronic device according to claim 9 , wherein the processor is configured to execute the computer program stored in the memory to perform the following operations:

rendering the video frame data by a main thread of a multimedia browsing application;

adding the first memory address to the memory multiplexing queue by the main thread.

17. A non-transitory computer-readable storage medium storing a computer program, the computer program, when executed by a processor, causes the processor to perform the following operations:

allocating a first memory address to video frame data based on a memory multiplexing queue, wherein the memory multiplexing queue records a memory address of video frame data that has been rendered;

storing the video frame data in a memory space indicated by the first memory address; and

adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data,

wherein the allocating a first memory address to video frame data based on a memory multiplexing queue comprises:

acquiring a second memory address from the memory multiplexing queue according to a data volume of the video frame data when the memory multiplexing queue comprises a memory address, wherein a memory space indicated by the second memory address is not less than the data volume of the video frame data; and

removing the second memory address from the memory multiplexing queue when the second memory address is acquired from the memory multiplexing queue, and taking the second memory address as the first memory address.