Semiconductor package structure and method for manufacturing the same

1. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die;

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die; and

a plurality of pillars extending through the encapsulant, wherein the portion is closer to the semiconductor die than each of the plurality of pillars is.

2. The semiconductor package structure of claim 1 , wherein a first one of the plurality of pillars and a second one of the plurality of pillars are disposed adjacent to a lateral side of semiconductor die, and a gap between the first one of the plurality of pillars and the second one of the plurality of pillars is greater than a horizontal gap between the portion and the semiconductor die.

3. The semiconductor package structure of claim 1 , wherein a horizontal gap between the portion and the semiconductor die is less than a horizontal gap between the portion and a first one of the plurality of pillars that is most adjacent to the portion than the others of the plurality of pillars.

4. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die; and

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die,

wherein a bottom surface of the portion is exposed to air and is substantially aligned with a bottom surface of the first passivation layer.

5. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die;

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die; and

a plurality of solder balls disposed under the first passivation layer, wherein a horizontal gap between the portion and a first one of the solder ball, that is most adjacent to the portion than the others of the plurality of solder balls, is greater than a horizontal gap between the portion and the semiconductor die.

6. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die; and

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die,

wherein the alignment mark is defined by a first through-hole within the portion, wherein a portion of the first passivation layer is disposed in the first through-hole and is exposed to air.

7. The semiconductor package structure of claim 6 , wherein a bottom surface of the portion of the first patterned layer and a bottom surface of the portion of the first passivation layer are substantially aligned with each other and are exposed to air.

8. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die; and

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die,

wherein a first part of the portion extends along a first side of the semiconductor die, and a second part of the portion extends along a second side of the semiconductor die from a top view perspective.

9. A semiconductor package structure, comprising:

a first passivation layer;

a semiconductor die disposed over the first passivation layer;

a first patterned layer disposed within the first passivation layer, wherein a portion of the first patterned layer is configured to serve as an alignment mark during a disposing process of the semiconductor die;

an encapsulant continuously encapsulating a lateral surface and a top surface of the semiconductor die,

a second passivation layer disposed under the first passivation layer; and

a second patterned layer disposed within the second passivation layer, wherein a portion of the second patterned layer is configured to serve as an alignment mark during the disposing process of the semiconductor die.

10. The semiconductor package structure of claim 9 , wherein a lateral surface of the portion of the second patterned layer is substantially aligned with a lateral surface of the portion of the first patterned layer.

11. A semiconductor package structure, comprising:

a passivation layer;

a first semiconductor die disposed over the passivation layer;

a first metal layer disposed within the passivation layer, wherein a portion of the first metal layer is configured to serve as an alignment mark during a disposing process of the first semiconductor die;

a redistribution structure disposed over the first semiconductor die;

a second semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure; and

a third semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure,

wherein the second semiconductor die is electrically connected to the third semiconductor die through the first semiconductor die.

12. A semiconductor package structure, comprising:

a passivation layer;

a first semiconductor die disposed over the passivation layer;

a first metal layer disposed within the passivation layer, wherein a portion of the first metal layer is configured to serve as an alignment mark during a disposing process of the first semiconductor die;

a redistribution structure disposed over the first semiconductor die;

a second semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure;

a third semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure;

a first underfill connecting the second semiconductor die and the redistribution structure, and having a lateral surface extending from a lateral surface of the second semiconductor die to a top surface of the redistribution structure and inclined toward the third semiconductor die; and

a second underfill connecting the third semiconductor die and the redistribution structure, and having a lateral surface extending from a lateral surface of the third semiconductor die to the top surface of the redistribution structure and inclined toward the second semiconductor die.

13. The semiconductor package structure of claim 12 , further comprising:

an encapsulant disposed between the second semiconductor die and the third semiconductor die, and contacting the lateral surface of the first underfill and the lateral surface of the second underfill.

14. A semiconductor package structure, comprising:

a passivation layer;

a first semiconductor die disposed over the passivation layer;

a first metal layer disposed within the passivation layer, wherein a portion of the first metal layer is configured to serve as an alignment mark during a disposing process of the first semiconductor die;

a redistribution structure disposed over the first semiconductor die;

a second semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure;

a third semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure; and

an encapsulant encapsulating at least two lateral surfaces of the second semiconductor die and at least two lateral surfaces of the third semiconductor die,

wherein the encapsulant encapsulates a top surface of the second semiconductor die and a top surface of the third semiconductor die.

15. A semiconductor package structure, comprising:

a passivation layer;

a first semiconductor die disposed over the passivation layer;

a first metal layer disposed within the passivation layer, wherein a portion of the first metal layer is configured to serve as an alignment mark during a disposing process of the first semiconductor die;

a redistribution structure disposed over the first semiconductor die;

a second semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure;

a third semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure; and

a plurality of first pillars connecting to the redistribution structure and the first metal layer, wherein, in a cross-sectional view, the plurality of first pillars are vertically overlapped with the second semiconductor die.

16. The semiconductor package structure of claim 15 , further comprising:

a plurality of second pillars connecting to the redistribution structure and the first metal layer, wherein, in the cross-sectional view, the plurality of second pillars are vertically overlapped with the third semiconductor die.

17. A semiconductor package structure, comprising:

a passivation layer;

a first semiconductor die disposed over the passivation layer;

a first metal layer disposed within the passivation layer, wherein a portion of the first metal layer is configured to serve as an alignment mark during a disposing process of the first semiconductor die;

a redistribution structure disposed over the first semiconductor die;

a second semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure; and

a third semiconductor die disposed over the redistribution structure, and electrically connected to the first semiconductor die through the redistribution structure,

wherein the portion of the first metal layer is vertically overlapped with the second semiconductor die.