Oscillation circuit, semiconductor device for oscillation circuit and method for manufacturing the same

1. An oscillation circuit, comprising:

a first inverting circuit having a first transistor of a first type, a second transistor of the first type, a third transistor of a second type, and a fourth transistor of the second type; wherein

the first transistor and the third transistor share a first gate region;

the second transistor and the fourth transistor share a second gate region;

the first transistor and the second transistor share a first source/drain region devoid of a pinout terminal and sandwiched by the first gate region and the second gate region; and

the third transistor and the fourth transistor share a second source/drain region devoid of a pinout terminal and sandwiched by the first gate region and the second gate region.

2. The oscillation circuit of claim 1 , wherein a gate terminal of the first transistor is connected to a gate terminal of the second transistor, and a gate terminal of the third transistor is connected to a gate terminal of the fourth transistor.

3. The oscillation circuit of claim 2 , wherein a drain terminal of the third transistor is connected to a source terminal of the second transistor, and a source terminal of the third transistor is connected to a drain terminal of the fourth transistor.

4. The oscillation circuit of claim 1 , further comprising a second inverting circuit, wherein the second inverting circuit has a fifth transistor of the first type and a sixth transistor of the first type, and a gate terminal of the fifth transistor is connected to a gate terminal of the sixth transistor.

5. The oscillation circuit of claim 4 , wherein the second inverting circuit further comprises a seventh transistor of a second type and an eighth transistor of the second type, and a gate terminal of the seventh transistor is connected to a gate terminal of the eighth transistor.

6. The oscillation circuit of claim 5 , wherein a drain terminal of the seventh transistor is connected to a source terminal of the sixth transistor, and a source terminal of the seventh transistor is connected to a drain terminal of the eighth transistor.

7. The oscillation circuit of claim 4 , wherein the aspect ratio of the first transistor is different from the aspect ratio of the fifth transistor.

8. The oscillation circuit of claim 4 , wherein the aspect ratio of the fifth transistor is in a range of 0.25˜0.5 times the aspect ratio of the first transistor.

9. The oscillation circuit of claim 4 , wherein the first inverting circuit is connected between a first node and a second node and the second inverting circuit is connected between the second node and a third node.

10. The oscillation circuit of claim 9 , further comprising a third inverting circuit connected between the third node and a fourth node and a fourth inverting circuit connected between the second node and the third node.

11. The oscillation circuit of claim 10 , wherein an output terminal of the first inverting circuit is connected to an output terminal of the second inverting circuit and an input terminal of the fourth inverting circuit.

12. The oscillation circuit of claim 10 , wherein an output terminal of the third inverting circuit is connected to an input terminal of the second inverting circuit and an output terminal of the fourth inverting circuit.

13. The oscillation circuit of claim 1 , wherein the first inverting circuit further comprises a number N of transistors of the first type connected between the first transistor and the second transistor, wherein

a gate terminal of each of the number N of transistors are electrically connected with each other;

two adjacent transistors of the number N of transistors share a common source/drain region, the common source/drain region being devoid of a pinout terminal; and

the number N is equal to or greater than two.

14. A semiconductor device for an inverting circuit in an oscillation circuit, comprising:

a first source/drain region sandwiched by a first gate region and a second gate region; and

a second source/drain region sandwiched by the first gate region and the second gate region; wherein

the first source/drain region is devoid of a pinout terminal, and

the second source/drain region is devoid of a pinout terminal.

15. The semiconductor device of claim 14 , further comprising a third source/drain region adjacent to the first gate region, the third source/drain region comprising a first pinout terminal.

16. The semiconductor device of claim 15 , further comprising a fourth source/drain region adjacent to the second gate region, the fourth source/drain region comprising a second pinout terminal.

17. The semiconductor device of claim 14 , wherein the second source/drain region and the first source/drain region are of different conductive types.

18. The semiconductor device of claim 14 , wherein the first gate region and the second gate region extend in parallel along a direction from the first source/drain region to the second source/drain region.

19. A method of manufacturing a semiconductor device for an oscillation circuit, comprising:

forming a first source/drain region of a first conductive type and a second source/drain region of a second conductive type different than the first conductive type;

forming a first gate region adjacent to a first side of both the first source/drain region and the second source/drain region;

forming a second gate region adjacent to a second side of both the first source/drain region and the second source/drain region;

wherein the first source/drain region is devoid of a pinout terminal, and

the first gate region and the second gate region extend in parallel along a direction from the first source/drain region to the second source/drain region.

20. The method of claim 19 , further comprising:

forming a third source/drain region adjacent to the first gate region, and

forming a first pinout terminal in contact with the third source/drain region.

21. The method of claim 19 , further comprising:

forming a third source/drain region adjacent to the second gate region, and forming a second pinout terminal in contact with the third source/drain region.