CTIA CMOS image sensor pixel with zero-biased multiplexer

1. A pixel circuit, comprising:

a plurality of photoelectric conversion devices;

a zero-biased multiplexer connected to the plurality of photoelectric conversion devices;

an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;

a capacitor disposed between the first input terminal and the output terminal; and

a reset switch disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch including a body terminal connected to a common reference voltage,

wherein the zero-biased multiplexer includes a pair of switches connected to each of the plurality of photoelectric conversion devices,

wherein a first switch of the pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the each of the plurality of photoelectric conversion devices, and

wherein a second electrode of the each of the plurality of photoelectric conversion devices is connected to a cathode voltage.

2. The pixel circuit according to claim 1 , wherein each of the plurality of photoelectric conversion devices receives a charge from an incident light, and the zero-biased multiplexer is configured to output a signal indicative of the charge that is received at the each of the plurality of photoelectric conversion devices to the amplifier.

3. The pixel circuit according to claim 1 , wherein the reset switch and the pair of switches connected to each of the plurality of photoelectric conversion devices are each a transistor.

4. The pixel circuit according to claim 1 , wherein the amplifier includes a second input terminal configured to receive a predetermined terminal voltage.

5. The pixel circuit according to claim 4 , wherein the predetermined terminal voltage is equal to the common reference voltage.

6. The pixel circuit according to claim 1 , wherein the common reference voltage is ground.

7. A pixel circuit, comprising:

a zero-biased multiplexer;

an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;

a capacitor disposed between the first input terminal and the output terminal;

a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor; and

a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer,

wherein the zero-biased multiplexer includes a first pair of switches connected to the first photoelectric conversion device and a second pair of switches connected to the second photoelectric conversion device,

wherein a first switch of the first pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the first photoelectric conversion device, wherein a first switch of the second pair of switches includes a first electrode connected to the first input terminal and a second electrode connected to a first electrode of the second photoelectric conversion device, and

wherein respective second electrodes of the first photoelectric conversion device and the second photoelectric conversion device are connected to a cathode voltage.

8. The pixel circuit according to claim 7 , wherein body terminals of the first pair of switches and body terminals of the second pair of switches are connected to a predetermined terminal voltage.

9. The pixel circuit according to claim 8 , wherein the predetermined terminal voltage is equal to the common reference voltage.

10. A pixel circuit, comprising:

a zero-biased multiplexer;

an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;

a capacitor disposed between the first input terminal and the output terminal;

a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor; and

a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer, wherein

the first reset transistor and the third reset transistor are connected in series between the first input terminal and the output terminal, and

one of a source terminal or a drain terminal of the second reset transistor is connected to a node between the first reset transistor and the third reset transistor.

11. The pixel circuit according to claim 10 , wherein the other of the source terminal or the drain terminal of the second reset transistor is connected to the common reference voltage.

12. The pixel circuit according to claim 7 , wherein the amplifier includes a second input terminal configured to receive a predetermined terminal voltage.

13. The pixel circuit according to claim 12 , wherein the predetermined terminal voltage is equal to the common reference voltage.

14. A pixel circuit, comprising:

a zero-biased multiplexer;

an amplifier including a first input terminal connected to the zero-biased multiplexer, and an output terminal;

a capacitor disposed between the first input terminal and the output terminal;

a reset switch network disposed between the first input terminal and the output terminal in parallel with the capacitor, the reset switch network including a first reset transistor with a first body terminal connected to a common reference voltage, a second reset transistor, and a third reset transistor; and

a plurality of pixels arranged in an array, a first pixel of the plurality of pixels including a first photoelectric conversion device that is connected to the zero-biased multiplexer, and a second pixel of the plurality of pixels including a second photoelectric conversion device that is connected to the zero-biased multiplexer, wherein

during a reset state of the pixel circuit, the first reset transistor is in a closed state, the second reset transistor is in an open state, and the third reset transistor is in the closed state, and

during an integration state of the first photoelectric conversion device, the first reset transistor is in the open state, the second reset transistor is in the closed state, and the third reset transistor is in the open state.

15. The pixel circuit according to claim 7 , wherein the first photoelectric conversion device and the second photoelectric conversion device each receives a charge from an incident light, and the zero-biased multiplexer is configured to output respective signals indicative of respective charges that are received to the amplifier.

16. The pixel circuit according to claim 7 , wherein the first reset transistor, the second reset transistor, and the third reset transistor are one of NMOS transistors or PMOS transistors, and wherein the zero-biased multiplexer includes a plurality of switches, each of the plurality of switches is one of a NMOS transistor or a PMOS transistor.