Gate driving circuit and electroluminescence display apparatus including the same
An electroluminescence display apparatus includes a display panel including a display area including a plurality of pixel lines and a non-display area including a gate driving circuit supplying a gate signal to the plurality of pixel lines, and each of the plurality of pixel lines includes a plurality of pixels, each of the plurality of pixels includes a pixel driving circuit and a light emitting device, each of the pixel driving circuit and the gate driving circuit is implemented with a p-type transistor and an n-type transistor, and the gate driving circuit supplies a gate signal to the n-type transistor of the pixel driving circuit, so that a stably output can be provided, and the non-display area of the display panel can be reduced.
1. A gate driving circuit comprising:
a pull-down unit controlled by a Q node to transfer a low level voltage to an output node;
a pull-up unit controlled by a QB node to transfer a high level voltage to the output node;
a Q node controller controlled by a first clock signal to transfer a start signal to the Q node; and
a QB node controller controlled by the Q node to transfer the high level voltage or the low level voltage to the QB node,
wherein the QB node controller comprises an n-type transistor and a p-type transistor connected to the Q node.
2. The gate driving circuit of claim 1 , wherein the pull-down unit and the pull-up unit are connected to the output node,
the pull-up unit comprises a first capacitor, and
the first capacitor is connected to the output node and the Q node.
3. The gate driving circuit of claim 1 , wherein the start signal has a high level voltage at a period corresponding to a four-horizontal period.
4. The gate driving circuit of claim 3 , wherein the first clock signal has a period of the four-horizontal period.
5. The gate driving circuit of claim 4 , wherein the first clock signal has a low level pulse which is shorter than half of the period and a high level pulse which is longer than half of the period.
6. The gate driving circuit of claim 4 , wherein a high level pulse of the first start signal overlaps a high level pulse and a low level pulse of the first clock signal.
7. The gate driving circuit of claim 4 , wherein the first clock signal has a first period which starts before the start signal is input to the Q node controller and a second period which starts after the start signal is input to the Q node controller,
the first period of the first clock signal starts with a low level voltage of the first clock signal and the start pulse has a low level voltage,
when the first clock signal has a high level voltage in the first period of the first clock signal, the start pulse is shifted from a low level voltage to a high level voltage, and
when the first clock signal has a high level voltage in the first period of the first clock signal, the start signal maintains the high level voltage.
8. The gate driving circuit of claim 7 , wherein the second period of the first clock signal starts based on a low level voltage, and the start signal starts based on the high level voltage, and
when the first clock signal has the high level voltage in the second period of the first clock signal, the start signal is shifted from a high level voltage to a low level voltage.
9. The gate driving circuit of claim 1 , wherein the start signal is an (n−2)th output signal of an (n−2)th gate signal generating circuit, when n is a natural number of 3 or more.
10. A gate driving circuit comprising:
a pull-down unit controlled by a Q node to transfer a low level voltage to an output node;
a pull-up unit controlled by a QB node to transfer a high level voltage to the output node;
a Q node controller controlled by a first clock signal to transfer a start signal to the Q node; and
a QB node controller controlled by the Q node to transfer the high level voltage or the low level voltage to the QB node,
wherein the QB node controller comprises n-type transistors.
11. The gate driving circuit of claim 10 , wherein the pull-down unit and the pull-up unit are connected to the output node,
the pull-up unit comprises a first capacitor, and
the first capacitor is connected to the output node and the Q node.
12. The gate driving circuit of claim 10 , wherein the start signal has a high level voltage at a period corresponding to a two-horizontal period.
13. The gate driving circuit of claim 12 , wherein the first clock signal has a period of the two-horizontal period.
14. The gate driving circuit of claim 13 , wherein the first clock signal has a high level pulse corresponding to a shorter period than a one-horizontal period and a low level pulse corresponding to a longer period than the one-horizontal period.
15. The gate driving circuit of claim 13 , wherein a high level pulse of the first start signal overlaps a high level pulse and a low level pulse of the first clock signal.
16. The gate driving circuit of claim 13 , wherein the first clock signal has a first period which starts before the start signal is input to the Q node controller and a second period which starts after the start signal is input to the Q node controller,
the first period of the first clock signal starts with a low level voltage of the first clock signal and the start pulse has a low level voltage,
when the first clock signal has a low level voltage, the start signal is shifted from a low level voltage to a high level voltage, and
when the first clock signal has a high level voltage in the first period of the first clock signal, the start signal maintains the high level voltage.
17. The gate driving circuit of claim 16 , wherein the second period of the first clock signal starts based on a low level voltage, and the start signal starts based on the high level voltage, and
when the first clock signal has the low level voltage in the second period of the first clock signal, the start signal is shifted from a high level voltage to a low level voltage.
18. The gate driving circuit of claim 10 , wherein the start signal is an (n−2)th output signal of an (n−2)th gate signal generating circuit, when n is a natural number of 3 or more.