Arsenic-doped epitaxial, source/drain regions for NMOS
Techniques are disclosed for providing an integrated circuit structure having NMOS transistors including an arsenic-doped interface layer between epitaxially grown source/drain regions and a channel region. The arsenic-doped interface layer may include, for example, arsenic-doped silicon (Si:As) having arsenic concentrations in a range of about 1E20 atoms per cm 3 to about 5E21 atoms per cm 3 . The interface layer may have a relatively uniform thickness in a range of about 0.5 nm to full fill where the entire source/drain region is composed of the Si:As. In cases where the arsenic-doped interface layer only partially fills the source/drain regions, another n-type doped semiconductor material can fill remainder (e.g., phosphorus-doped III-V compound or silicon). The use of a layer having a high arsenic concentration can provide improved NMOS performance in the form of abrupt junctions in the source/drain regions and highly conductive source/drain regions with negligible diffusion of arsenic into the channel region.
1. An integrated circuit structure, comprising:
a substrate;
a gate structure over the substrate, the gate structure being part of an NMOS transistor device; and
a source region and a drain region to respective sides of the gate structure, the source region and the drain region each including an arsenic-doped interface layer and a body, wherein the arsenic-doped interface layer of the source region is between the body of the source region and a channel region, wherein the arsenic-doped interface layer of the drain region is between the body of the drain region and the channel region, wherein the arsenic-doped interface layer of the source region completely separates the body of the source region from the substrate and the channel region, and wherein the arsenic-doped interface layer of the drain region completely separates the body of the drain region from the substrate and the channel region.
2. The integrated circuit structure of claim 1 , wherein the substrate is a bulk silicon substrate.
3. The integrated circuit structure of claim 1 , wherein the source region includes an undercut such that the source region extends under the gate structure and the drain region includes an undercut such that the source region extends under the gate structure.
4. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer is conformal.
5. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer includes an arsenic concentration in a range of 1E20 atoms per cm.sup.3 to 5E21 atoms per cm.sup.3.
6. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer includes arsenic-doped silicon comprising an arsenic concentration of 1E21 atoms per cm.sup.3, or higher.
7. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer has a thickness in a range of 0.5 nm to 25 nm.
8. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer and the body include arsenic-doped silicon comprising an arsenic concentration in a range of 1E20 atoms per cm 3 to 5E21 atoms per cm 3 .
9. The integrated circuit structure of claim 1 , wherein the arsenic-doped interface layer and the body include silicon co-doped with arsenic and phosphorus, such that the arsenic-doped interface layer is doped with arsenic and the body is doped with phosphorus.
10. The integrated circuit structure of claim 9 , wherein the arsenic-doped interface layer inhibits the phosphorus from migrating into the channel region under the gate structure.
11. The integrated circuit structure of claim 1 , wherein the body includes silicon doped with one or more of arsenic, phosphorus, and carbon.
12. The integrated circuit structure of claim 1 , wherein the NMOS transistor device has a planar transistor configuration.
13. The integrated circuit structure of claim 1 , wherein the NMOS transistor device has a non-planar transistor configuration.
14. The integrated circuit structure of claim 13 , wherein the non-planar transistor configuration includes a fin structure under the gate structure, and the gate structure is on multiple sides of the fin structure.
15. The integrated circuit structure of claim 13 , wherein the non-planar transistor configuration includes a nanowire and/or nanoribbon under the gate structure, and the gate structure wraps around the nanowire and/or nanoribbon.