Semiconductor device including a transistor with one or more barrier regions
A semiconductor device includes a transistor having a drift region of a first conductivity type in a semiconductor substrate having a first main surface, a body region of a second conductivity type between the drift region and first main surface, and trenches in the first main surface which pattern the substrate into mesas. The trenches include an active trench and first and second source trenches. A source region of the first conductivity type is in a first mesa arranged adjacent to the active trench. A second mesa between the first and second source trenches is in contact with at least one source trench. A barrier region of the first conductivity type at a higher doping concentration than the drift region is arranged between the body and drift regions in the second mesa. A vertical size of the barrier region is at least twice a width of the second mesa.
1. A semiconductor device comprising a transistor, the transistor comprising:
a drift region of a first conductivity type in a semiconductor substrate having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface;
a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas comprising a first mesa, the plurality of trenches comprising an active trench, a first source trench and a second source trench, wherein a conductive material in the first and second source trenches is connected to a source terminal;
a gate electrode arranged in the active trench;
a source region of the first conductivity type in the first mesa, the first mesa being arranged adjacent to the active trench;
a second mesa between the first and second source trenches, the second mesa being in contact with at least one of the first and the second source trenches; and
a barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region,
wherein the barrier region is arranged between the body region and the drift region,
wherein the barrier region is arranged in the second mesa,
wherein a vertical size of the barrier region is at least twice a width of the second mesa.
2. The semiconductor device of claim 1 , wherein the plurality of trenches further comprises a dummy trench between the first and second source trenches, and wherein dummy mesas are arranged on either sides of the dummy trench.
3. The semiconductor device of claim 2 , wherein a conductive material in the dummy trench is electrically connected to the source terminal.
4. The semiconductor device of claim 1 , wherein a width of the first mesa is less than 1 μm.
5. The semiconductor device of claim 1 , wherein the first mesa is arranged between the active trench and the first source trench.
6. The semiconductor device of claim 1 , wherein a ratio between the doping concentration of the barrier region and the doping concentration of the drift region is in a range of 100 to 10000.
7. The semiconductor device of claim 6 , wherein the doping concentration of the drift region varies, and wherein the ratio is a ratio between the doping concentration of the barrier region and a highest doping concentration of the drift region.
8. The semiconductor device of claim 1 , wherein the barrier region is arranged in direct contact with the drift region.
9. The semiconductor device of claim 8 , wherein an interface between the barrier region and the drift region forms a junction between portions of identical doping types having different doping concentrations.
10. The semiconductor device of claim 1 , wherein the barrier region is patterned.
11. The semiconductor device of claim 1 , wherein the barrier region extends from one sidewall of the second mesa to another sidewall of the second mesa in a horizontal direction.
12. A semiconductor device comprising a transistor, the transistor comprising:
a drift region of a first conductivity type in a semiconductor substrate having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface;
a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas comprising a first mesa and a second mesa, the plurality of trenches comprising an active trench;
a gate electrode arranged in the active trench;
a source region of the first conductivity type in at least one of the first mesa and the second mesa;
a first barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region, the first barrier region being disposed between the body region and the drift region, the first barrier region being disposed in the first mesa; and
a second barrier region of the first conductivity type having a lower doping concentration than the first barrier region and having a higher doping concentration than the drift region, the second barrier region being disposed between the body region and the drift region, the second barrier region being disposed in the second mesa.
13. The semiconductor device of claim 12 , wherein the source region is arranged in the first and the second mesas.
14. The semiconductor device of claim 12 , wherein the second mesa is a dummy mesa.
15. The semiconductor device of claim 12 , wherein the first mesa is arranged adjacent to a first side of the active trench and the second mesa is arranged adjacent to a second side of the active trench opposite the first side.
16. The semiconductor device of claim 12 , wherein a ratio between the doping concentration of the first barrier region and the doping concentration of the drift region is in a range of 100 to 10000.
17. The semiconductor device of claim 12 , wherein the first barrier region is arranged in direct contact with the drift region.
18. The semiconductor device of claim 12 , wherein the first barrier region is patterned.
19. The semiconductor device of claim 12 , wherein the first barrier region extends from one sidewall of the first mesa to another sidewall of the first mesa in a horizontal direction.
20. The semiconductor device of claim 12 , wherein the second barrier region extends from one sidewall of the second mesa to another sidewall of the second mesa in a horizontal direction.