Semiconductor device having a transistor with trenches and mesas
A semiconductor device includes a transistor that has: a drift region of a first conductivity type in a semiconductor substrate having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas including a first mesa and a plurality of dummy mesas, the plurality of trenches including an active trench and a plurality of dummy trenches arranged in a row; a gate electrode arranged in the active trench; and a source region of the first conductivity type in the first mesa. The first mesa is arranged adjacent to the active trench. A dummy mesa is arranged between each adjacent pair of the dummy trenches. The dummy mesas do not carry load current during an on-state of the transistor.
1. A semiconductor device comprising a transistor, the transistor comprising:
a drift region of a first conductivity type in a semiconductor substrate having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface;
a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas comprising a first mesa, the plurality of trenches comprising an active trench, a first source trench and a second source trench, wherein a conductive material in the first and second source trenches is electrically connected to a source terminal;
a gate electrode arranged in the active trench;
a source region of the first conductivity type in the first mesa, the first mesa being arranged adjacent to the active trench;
a second mesa between the first and second source trenches, the second mesa being in contact with at least one of the first and the second source trenches; and
a barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region,
wherein the barrier region is arranged between the body region and the drift region in the second mesa.
2. The semiconductor device of claim 1 , wherein the plurality of trenches further comprises a dummy trench between the first and second source trenches, and wherein dummy mesas are arranged on either sides of the dummy trench.
3. The semiconductor device of claim 2 , wherein a conductive material in the dummy trench is electrically connected to the source terminal.
4. The semiconductor device of claim 1 , wherein a width of the first mesa is less than 1 μm.
5. The semiconductor device of claim 1 , wherein the first mesa is arranged between the active trench and the first source trench.
6. The semiconductor device of claim 1 , wherein a ratio between the doping concentration of the barrier region and the doping concentration of the drift region is in a range of 100 to 10000.
7. The semiconductor device of claim 6 , wherein the doping concentration of the drift region varies, and wherein the ratio is a ratio between the doping concentration of the barrier region and a highest doping concentration of the drift region.
8. The semiconductor device of claim 1 , wherein the barrier region is arranged in direct contact with the drift region.
9. The semiconductor device of claim 8 , wherein an interface between the barrier region and the drift region forms a junction between portions of identical doping types having different doping concentrations.
10. The semiconductor device of claim 1 , wherein the barrier region is patterned.
11. The semiconductor device of claim 1 , wherein the barrier region extends from one sidewall of the second mesa to another sidewall of the second mesa in a horizontal direction.
12. A semiconductor device comprising a transistor, the transistor comprising:
a drift region of a first conductivity type in a semiconductor substrate having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface;
a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas comprising a first mesa, the plurality of trenches comprising an active trench, a first source trench and a second source trench, wherein a conductive material in the first and second source trenches is electrically connected to a source terminal;
a gate electrode arranged in the active trench;
a source region of the first conductivity type in the first mesa, the first mesa being arranged adjacent to the active trench;
a second mesa between the first and second source trenches, the second mesa being in contact with at least one of the first and the second source trenches; and
a barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region,
wherein the barrier region is arranged between the body region and the drift region in the first mesa.
13. The semiconductor device of claim 12 , further comprising:
an additional barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region,
wherein the additional barrier region is arranged between the body region and the drift region in the second mesa.
14. The semiconductor device of claim 13 , wherein the additional barrier region in the second mesa has a lower doping concentration than the barrier region in the first mesa.
15. The semiconductor device of claim 13 , wherein the second mesa is devoid of a source region of the first conductivity type.
16. The semiconductor device of claim 12 , wherein the second mesa is devoid of a barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region.
17. A semiconductor device comprising a transistor, the transistor comprising:
a drift region of a first conductivity type in a semiconductor substrate having a first main surface;
a body region of a second conductivity type between the drift region and the first main surface;
a plurality of trenches in the first main surface and patterning the semiconductor substrate into a plurality of mesas comprising a first mesa and a plurality of dummy mesas, the plurality of trenches comprising an active trench and a plurality of dummy trenches arranged in a row;
a gate electrode arranged in the active trench; and
a source region of the first conductivity type in the first mesa,
wherein the first mesa is arranged adjacent to the active trench,
wherein a dummy mesa is arranged between each adjacent pair of the dummy trenches,
wherein the dummy mesas do not carry load current during an on-state of the transistor.
18. The semiconductor device of claim 17 , wherein a conductive material in the plurality of dummy trenches is electrically connected to a source terminal or a gate terminal.
19. The semiconductor device of claim 17 , wherein the plurality of dummy trenches comprises at least three dummy trenches arranged adjacent to each other.
20. The semiconductor device of claim 17 , further comprising:
a barrier region of the first conductivity type at a higher doping concentration than the doping concentration of the drift region,
wherein the barrier region is arranged between the body region and the drift region in the dummy mesas.