Epitaxial features confined by dielectric fins and spacers
A semiconductor device includes a substrate, a dielectric isolation structure disposed on the substrate, a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure, first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin, a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins, and an epitaxial feature over the semiconductor fin. The epitaxial feature has a bottom portion laterally between the first and second dielectric fins.
1. A semiconductor device, comprising:
a substrate;
a dielectric isolation structure disposed on the substrate;
a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure;
first and second dielectric fins disposed on the dielectric isolation structure and sandwiching the semiconductor fin;
a dielectric block disposed on the substrate and interfacing with the first and second dielectric fins; and
an epitaxial feature over the semiconductor fin, wherein the epitaxial feature has a bottom portion laterally between the first and second dielectric fins.
2. The semiconductor device of claim 1 , wherein the dielectric block interfaces with the semiconductor fin.
3. The semiconductor device of claim 1 , further comprising:
a gate stack disposed on the semiconductor fin; and
a spacer layer over sidewalls of the gate stack, wherein the spacer layer is laterally between the semiconductor fin and each of the first and second dielectric fins.
4. The semiconductor device of claim 3 , further comprising:
an oxide layer disposed on the dielectric isolation structure, wherein the oxide layer is laterally between the spacer layer and each of the first and second dielectric fins.
5. The semiconductor device of claim 1 , wherein the epitaxial feature has a top portion above the first and second dielectric fins.
6. The semiconductor device of claim 5 , wherein the top portion of the epitaxial feature has a faceted sidewall.
7. The semiconductor device of claim 5 , wherein the top portion of the epitaxial feature has a larger width than the bottom portion of the epitaxial feature.
8. The semiconductor device of claim 1 , wherein the bottom portion of the epitaxial feature has a vertical sidewall.
9. The semiconductor device of claim 1 , wherein the bottom portion of the epitaxial feature has a tapering sidewall.
10. The semiconductor device of claim 1 , wherein the first and second dielectric fins have different heights.
11. A semiconductor device, comprising:
a substrate;
a dielectric isolation structure disposed on the substrate;
a semiconductor fin disposed on the substrate and extending through the dielectric isolation structure;
a dielectric fin disposed on the dielectric isolation structure;
an epitaxial feature over the semiconductor fin; and
a spacer feature sandwiched between the epitaxial feature and the dielectric fin, wherein the spacer feature has a tapering sidewall facing the epitaxial feature and a vertical sidewall facing the dielectric fin.
12. The semiconductor device of claim 11 , wherein the tapering sidewall of the spacer feature interfaces with the epitaxial feature.
13. The semiconductor device of claim 12 , wherein the vertical sidewall of the spacer feature interfaces with the dielectric fin.
14. The semiconductor device of claim 12 , wherein the vertical sidewall of the spacer feature is distant from the dielectric fin.
15. The semiconductor device of claim 14 , further comprising:
a dielectric layer sandwiched between the dielectric fin and the vertical sidewall of the spacer feature.
16. The semiconductor device of claim 11 , further comprising:
a conductor disposed on the epitaxial feature,
wherein a top portion of the dielectric fin protrudes into a bottom portion of the conductor.
17. A semiconductor device, comprising:
a substrate;
a dielectric isolation structure disposed on the substrate;
first and second semiconductor fins disposed on the substrate and extending through the dielectric isolation structure;
first and second epitaxial features over the first and second semiconductor fins respectively;
a dielectric fin disposed on the dielectric isolation structure and sandwiched between the first and second epitaxial features; and
a contact feature interfacing with the dielectric fin and the first and second epitaxial features,
wherein the dielectric fin is above the first and second epitaxial features.
18. The semiconductor device of claim 17 , wherein a bottom portion of the dielectric fin is embedded in the dielectric isolation structure.
19. The semiconductor device of claim 17 , wherein the second epitaxial feature is above the first epitaxial feature.
20. The semiconductor device of claim 17 , wherein each of the first and second epitaxial features has tapering sidewalls.