IP Library Granted Patent US 11,611,400
Granted Patent B2
US 11,611,400 · App. 17/160,631 · Granted Mar 21, 2023

Array antenna system, and calibration method and apparatus thereof

Inventors: Sunwoo Kong (Daejeon, KR); Kwang Seon Kim (Sejong-si, KR); Jeehoon Park (Daejeon, KR); Hui Dong Lee (Daejeon, KR); Seunghyun Jang (Daejeon, KR); Seok Bong Hyun (Daejeon, KR)
Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
H04B17/12H01Q3/267H04B17/14H04B17/21
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Quick Facts
Patent No.
US 11,611,400
App. No.
17/160,631
Granted
Mar 21, 2023
Kind
B2
Abstract

An array antenna system, and a calibration method and apparatus thereof are provided. The calibration method includes measuring a signal loop including mutual coupling between antennas included in an array antenna, calculating a ratio of a reception (RX) signal received by each antenna to an RX signal received by a reference antenna of the array antenna based on a result of the measuring, and performing calibration of the array antenna based on the ratio.

Claims (28)

1. An array antenna calibration system comprising:

a plurality of transceiver units each including:

a common transmission (TX) port and a common reception (RX) port,

a plurality of antennas arranged in a lattice form, and

a transceiver,

wherein the plurality of transceiver units are arranged in a lattice form, and adjacent ones of the plurality of transceiver units are mutually coupled to each other to generate signal loops;

a first power combiner configured to combine the common TX ports of the plurality of transceiver units and connect the combined common TX ports to a transceiver chip;

a second power combiner configured to combine the common RX ports of the plurality of transceiver units and connect the combined common RX ports to the transceiver chip;

a processor configured to measure the signal loops and to calculate a ratio of a reception (RX) signal received by each antenna to an RX signal received by a reference antenna based on a result of the measuring; and

a calibration circuit configured to perform calibration based on the ratio.

2. The array antenna calibration system of claim 1 , wherein the processor is configured to measure a signal loop comprising an antenna connected to a transceiver in a transmission (TX) mode and an antenna connected to a transceiver in an RX mode.

3. The array antenna calibration system of claim 1 , wherein:

the processor is configured to measure a first signal loop and a second signal loop in which a second antenna and a third antenna receive signals transmitted by a first antenna through mutual coupling, to measure a third signal loop and a fourth signal loop in which the second antenna and the third antenna receive signals transmitted by a fourth antenna through mutual coupling, and to calculate a ratio of an RX signal received by the third antenna to an RX signal received by the second antenna based on results obtained by measuring the first signal loop through the fourth signal loop.

4. The array antenna calibration system of claim 1 , wherein the calibration circuit comprises:

a gain/attenuator circuit configured to perform calibration of an amplitude based on the ratio; and

a phase shifter configured to perform calibration of a phase based on the ratio.

5. The array antenna calibration system of claim 1 , wherein the calibration circuit is configured to perform row calibration of antennas of each of rows in the plurality of transceiver units based on a first antenna of each of the rows, and to perform column calibration of first antennas of the rows.

6. An array antenna system comprising:

a plurality of transceiver units each including a common transmission (TX) port and a common reception (RX) port, wherein the plurality of transceiver units are arranged in a lattice form, and adjacent ones of the plurality of transceiver units are mutually coupled to each other to generate signal loops;

a first power combiner configured to combine the common TX ports of the plurality of transceiver units and connect the combined common TX ports to a transceiver chip; and

a second power combiner configured to combine the common RX ports of the plurality of transceiver units and connect the combined common RX ports to the transceiver chip,

wherein each of the plurality of transceiver units comprises:

a plurality of antennas arranged in a lattice form; and

a transceiver.

7. The array antenna system of claim 6 , wherein the transceiver comprises:

a plurality of switches configured to select a path connected to each of the antennas; and

a power combiner configured to combine the selected paths and to connect the combined paths to the common TX port or the common RX port.

8. The array antenna system of claim 6 , wherein the plurality of antennas comprise patch antennas arranged at vertices.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2021
From: KONG, SUNWOO; KIM, KWANG SEON; PARK, JEEHOON; LEE, HUI DONG; JANG, SEUNGHYUN; HYUN, SEOK BONG
To: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
Reel/Frame 055060/0385 →
Priority Claims (1)
KR 10-2020-0011100 · Jan 30, 2020 · national
Continuity (1)
Related Publication 20210242948A1 · Aug 5, 2021
Cited By (1)
US 12,725,927