Translation lookaside buffer to implement adapative page size
Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.
1. A computer implemented method, comprising:
reserving a block of physical memory communicatively coupled to a processor;
allocating a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size;
generating an entry in a transaction lookaside buffer (TLB) entry for the single memory page, the TLB entry comprising a physical page number (PPN), a tag, an extensible page size indicator (ESI) field, and an actual page size indicator (ASI) field; and
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold:
allocating additional memory to the first portion of the block of physical memory; and
increasing the single memory page from a first page size to a second page size.
2. The method of claim 1 , further comprising:
implementing a single addressing scheme for the first portion of the block of physical memory.
3. The method of claim 1 , wherein:
the first page size is 4 KB; and
the second page size is 8 KB.
4. The method of claim 1 , further comprising:
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a second threshold:
allocating additional memory to the first portion of the block of physical memory; and
increasing the single memory page from a second page size to a third page size.
5. A non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:
reserving a block of physical memory communicatively coupled to a processor;
allocating a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size;
generating an entry in a transaction lookaside buffer (TLB) entry for the single memory page, the TLB entry comprising a physical page number (PPN), a tag, an extensible page size indicator (ESI) field, and an actual page size indicator (ASI) field; and
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold:
allocating additional memory to the first portion of the block of physical memory; and
increasing the single memory page from a first page size to a second page size.
6. The non-transitory machine readable medium of claim 5 , the operations additionally comprising:
implementing a single addressing scheme for the first portion of the block of physical memory.
7. The non-transitory machine readable medium of claim 5 , wherein:
the first page size is 4 KB; and
the second page size is 8 KB.
8. The non-transitory machine readable medium of claim 5 , the operations additionally comprising:
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a second threshold:
allocating additional memory to the first portion of the block of physical memory; and
increasing the single memory page from a second page size to a third page size.
9. An electronic device, comprising:
a processor to:
reserve a block of physical memory communicatively coupled to a processor;
allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size;
generating an entry in a transaction lookaside buffer (TLB) entry for the single memory page, the TLB entry comprising a physical page number (PPN), a tag, an extensible page size indicator (ESI) field, and an actual page size indicator (ASI) field; and
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold:
allocate additional memory to the first portion of the block of physical memory; and
increase the single memory page from a first page size to a second page size; and
a memory communicatively coupled to the processor.
10. The electronic device of claim 9 , the processor to:
implement a single addressing scheme for the first portion of the block of physical memory.
11. The electronic device of claim 9 , wherein:
the first page size is 4 KB; and
the second page size is 8 KB.
12. The electronic device of claim 9 , the processor to:
in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a second threshold:
allocating additional memory to the first portion of the block of physical memory; and
increasing the single memory page from a second page size to a third page size.