Enhancement on-state power semiconductor device characteristics utilizing new cell geometries
View Patent ↗A semiconductor device and a method of making thereof are disclosed. The device includes a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type formed on the substrate. A buffer layer between the substrate and the epitaxial layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer. A cell includes a body region doped with the second conductivity formed in the epitaxial layer. The second conductivity type is opposite the first conductivity type. The cell includes a source region doped with the first conductivity type and formed in at least the body region. The device further includes a short region doped with the second conductivity type formed in the epitaxial layer separated from source region of the cell by the body region of the cell wherein the short region is conductively coupled with the source region.
1. A semiconductor device comprising:
a substrate heavily doped with a first conductivity type
an epitaxial layer lightly doped with the first conductivity type formed on the substrate;
a buffer layer between the substrate and the epitaxial layer, wherein the buffer layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer;
a cell, the cell including:
a body region doped with a second conductivity type formed in the epitaxial layer, wherein the second conductivity type is opposite the first conductivity type;
a source region doped with the first conductivity type formed in at least the body region;
the device further including:
a short region doped with the second conductivity type formed in the epitaxial layer separated from source region of the cell by the body region of the cell;
an insulating layer formed over the short region, the body region, and the source region;
wherein the short region is conductively coupled to the source region by a short contact electrically connected to the short region through the insulation layer, a source contact electrically connected to the source region through the insulation layer, and a power metal layer electrically connected between the short contact and the source contact, wherein the power metal layer is formed over the insulation layer.
2. The semiconductor device of claim 1 wherein the body region of the cell is in ohmic contact with the short region.
3. The semiconductor device of claim 2 wherein a JFET region of the epitaxial layer separates a portion of the short region from the body region of the cell and a strip of the short region interrupts the JFET region wherein the strip of the short region makes ohmic contact with the body region of the cell.
4. The semiconductor device of claim 3 comprising more than one cell wherein the short region is shared between two or more cells.
5. The semiconductor device of claim 3 wherein the strip of the short region is a width sufficient for a current to travel to the body region from the short region.
6. The semiconductor device of claim 1 further comprising more than one cell wherein the short region is shared between two or more cells.
7. The semiconductor device of claim 6 wherein each cell of the more than one cells is separated by a JFET region wherein the width of the JFET region is chosen to have a sufficient low on-resistance and reduced electric field across the gate oxide.
8. The semiconductor device of claim 1 comprising a gate formed over the epitaxial layer and a portion of the body region.
9. The semiconductor device of claim 8 wherein the gate comprises an insulating layer formed on top of the epitaxial layer and a conductive layer formed on top of the insulating layer.
10. The semiconductor device of claim 1 wherein a material of the source contact is different than a material of the short contact.
11. The semiconductor device of claim 10 wherein the material of the source contact is a metal and wherein the material of the short contact is a metal and wherein the metal of source contact is different than the metal of the short contact.
12. A method of making a semiconductor device comprising:
forming a cell by
forming a body region in an epitaxial layer lightly doped with a first conductivity type formed on a substrate heavily doped with the first conductivity type with a buffer layer between the substrate and the epitaxial layer, wherein the buffer layer is doped with the first conductivity type at a doping level between that of the substrate and that of the epitaxial layer, wherein the body region is doped with a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, and
forming a source region doped with the first conductivity type in at least the body region;
forming a short region in the epitaxial layer, wherein the short region is doped with the second conductivity type, wherein the short region is separated from source region of the cell by the body region of the cell;
forming an insulating layer over the short region, the body region, and the source region; and
forming a short contact electrically connected to the short region through the insulation layer, a source contact electrically connected to the source region through the insulation layer, and a power metal layer electrically connected between the short contact and the source contact, wherein the power metal layer is formed over the insulation layer, whereby the short region is conductively coupled to the source region.
13. The method of claim 12 wherein the body region of the cell is in ohmic contact with the short region.
14. The method of claim 13 wherein a JFET region of the epitaxial layer separates a portion of the short region from the body region of the cell, the method further comprising
forming a strip of the short region that interrupts the JFET region wherein the strip of the short region makes ohmic contact with the body region of the cell.
15. The method of claim 14 further comprising forming more than one cell wherein the short region is shared between the more than one cell.
16. The method of claim 14 wherein the strip of the short region is a width sufficient for a current to travel to the body region from the short region.
17. The method of claim 12 further comprising forming more than one cell wherein the short region is shared between the more than one cell.
18. The method of claim 17 wherein each cell of the more than one cells is separated by a JFET region wherein the width of the JFET region is chosen to have a sufficient low on-resistance and reduced electric field across the gate oxide.
19. The method of claim 12 comprising forming a gate over the epitaxial layer and a portion of the body region.
20. The method of claim 19 wherein forming the gate comprises creating an insulating layer on top of the epitaxial layer and a forming a conductive layer formed on top of the insulating layer.
21. The method of claim 19 wherein a material of the source contact is different than a material of the short contact.
22. The method of claim 21 wherein the material of the source contact is a metal and wherein the material of the short contact is a metal and wherein the metal of source contact might be different than the metal of the short contact.